Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-30 Thread Dan Williams
On Tue, Jun 30, 2020 at 8:09 PM Aneesh Kumar K.V wrote: > > On 7/1/20 1:15 AM, Dan Williams wrote: > > On Tue, Jun 30, 2020 at 2:21 AM Aneesh Kumar K.V > > wrote: > > [..] > The bio argument isn't for range based flushing, it is for flush > operations that need to complete

Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-30 Thread Aneesh Kumar K.V
On 7/1/20 1:15 AM, Dan Williams wrote: On Tue, Jun 30, 2020 at 2:21 AM Aneesh Kumar K.V wrote: [..] The bio argument isn't for range based flushing, it is for flush operations that need to complete asynchronously. How does the block layer determine that the pmem device needs asynchronous

Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-30 Thread Dan Williams
On Tue, Jun 30, 2020 at 2:21 AM Aneesh Kumar K.V wrote: [..] > >> The bio argument isn't for range based flushing, it is for flush > >> operations that need to complete asynchronously. > > How does the block layer determine that the pmem device needs > > asynchronous fushing? > > > >

Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-30 Thread Aneesh Kumar K.V
On 6/30/20 2:24 PM, Michal Suchánek wrote: On Mon, Jun 29, 2020 at 06:50:15PM -0700, Dan Williams wrote: On Mon, Jun 29, 2020 at 1:41 PM Aneesh Kumar K.V wrote: Michal Suchánek writes: Hello, On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote: nvdimm expect the flush

Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-30 Thread Michal Suchánek
On Mon, Jun 29, 2020 at 06:50:15PM -0700, Dan Williams wrote: > On Mon, Jun 29, 2020 at 1:41 PM Aneesh Kumar K.V > wrote: > > > > Michal Suchánek writes: > > > > > Hello, > > > > > > On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote: > > >> nvdimm expect the flush routines to just

Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-29 Thread Dan Williams
On Mon, Jun 29, 2020 at 1:41 PM Aneesh Kumar K.V wrote: > > Michal Suchánek writes: > > > Hello, > > > > On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote: > >> nvdimm expect the flush routines to just mark the cache clean. The barrier > >> that mark the store globally visible is

Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-29 Thread Aneesh Kumar K.V
Michal Suchánek writes: > Hello, > > On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote: >> nvdimm expect the flush routines to just mark the cache clean. The barrier >> that mark the store globally visible is done in nvdimm_flush(). >> >> Update the papr_scm driver to a

Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-29 Thread Michal Suchánek
Hello, On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote: > nvdimm expect the flush routines to just mark the cache clean. The barrier > that mark the store globally visible is done in nvdimm_flush(). > > Update the papr_scm driver to a simplified nvdim_flush callback that do >

[PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines

2020-06-29 Thread Aneesh Kumar K.V
nvdimm expect the flush routines to just mark the cache clean. The barrier that mark the store globally visible is done in nvdimm_flush(). Update the papr_scm driver to a simplified nvdim_flush callback that do only the required barrier. Signed-off-by: Aneesh Kumar K.V ---