Hello Dave,
On Tue, Sep 25, 2018 at 03:16:30PM -0700, Dave Hansen wrote:
> On 09/22/2018 04:03 AM, Gautham R Shenoy wrote:
> > Without this patchset, the SMT domain would be defined as the group of
> > threads that share L2 cache.
>
> Could you try to make a more clear, concise statement about
On 09/22/2018 04:03 AM, Gautham R Shenoy wrote:
> Without this patchset, the SMT domain would be defined as the group of
> threads that share L2 cache.
Could you try to make a more clear, concise statement about the current
state of the art vs. what you want it to be? Right now, the sched
Hi Dave,
On Thu, Sep 20, 2018 at 11:04:54AM -0700, Dave Hansen wrote:
> On 09/20/2018 10:22 AM, Gautham R. Shenoy wrote:
> >-
> >|L1 Cache |
> >--
> >|L2| | | | |
> >| |
On 09/20/2018 10:22 AM, Gautham R. Shenoy wrote:
> -
> |L1 Cache |
>--
>|L2| | | | |
>| | 0 | 2 | 4 | 6 |Small Core0
>|C | | | | |
>
From: "Gautham R. Shenoy"
Hi,
This is the eight iteration of the patchset to add support for
big-core on POWER9. This patch also optimizes the task placement on
such big-core systems.
The previous versions can be found here:
v7: https://lkml.org/lkml/2018/8/20/52
v6:
