[RFC PATCH v2 06/10] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache

[Claudio Carvalho]

From: Ram Pai <linux...@us.ibm.com>

Ultravisor is responsible for flushing the tlb cache, since it manages
the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
available.

Signed-off-by: Ram Pai <linux...@us.ibm.com>
Signed-off-by: Claudio Carvalho <cclau...@linux.ibm.com>
---
 arch/powerpc/mm/book3s64/pgtable.c | 33 +++++++++++++++++-------------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/mm/book3s64/pgtable.c 
b/arch/powerpc/mm/book3s64/pgtable.c
index 40a9fc8b139f..1eeb5fe87023 100644
--- a/arch/powerpc/mm/book3s64/pgtable.c
+++ b/arch/powerpc/mm/book3s64/pgtable.c
@@ -224,6 +224,23 @@ void __init mmu_partition_table_init(void)
        powernv_set_nmmu_ptcr(ptcr);
 }
 
+static void flush_partition(unsigned int lpid, unsigned long dw0)
+{
+       if (dw0 & PATB_HR) {
+               asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
+                            "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
+               asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
+                            "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
+               trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
+       } else {
+               asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
+                            "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
+               trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
+       }
+       /* do we need fixup here ?*/
+       asm volatile("eieio; tlbsync; ptesync" : : : "memory");
+}
+
 static void __mmu_partition_table_set_entry(unsigned int lpid,
                                            unsigned long dw0,
                                            unsigned long dw1)
@@ -238,20 +255,8 @@ static void __mmu_partition_table_set_entry(unsigned int 
lpid,
         * The type of flush (hash or radix) depends on what the previous
         * use of this partition ID was, not the new use.
         */
-       asm volatile("ptesync" : : : "memory");
-       if (old & PATB_HR) {
-               asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
-                            "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
-               asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
-                            "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
-               trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
-       } else {
-               asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
-                            "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
-               trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
-       }
-       /* do we need fixup here ?*/
-       asm volatile("eieio; tlbsync; ptesync" : : : "memory");
+       if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR))
+               flush_partition(lpid, old);
 }
 
 void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
-- 
2.20.1