Re: 答复: [v7] clk: corenet: Adds the clock binding
On Wed, 2014-01-08 at 20:57 -0600, Tang Yuantian-B29983 wrote: Thanks for you review. See my response inline. Thanks, Yuantian -Original Message- From: Wood Scott-B07421 Sent: 2014年1月9日 星期四 2:44 To: Mark Rutland Cc: Tang Yuantian-B29983; ga...@kernel.crashing.org; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org Subject: Re: 答复: [v7] clk: corenet: Adds the clock binding On Wed, 2014-01-08 at 09:30 +, Mark Rutland wrote: On Wed, Jan 08, 2014 at 08:53:56AM +, Yuantian Tang wrote: 发件人: Wood Scott-B07421 发送时间: 2014年1月8日 8:21 收件人: Tang Yuantian-B29983 抄送: ga...@kernel.crashing.org; mark.rutl...@arm.com; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org 主题: Re: [v7] clk: corenet: Adds the clock binding On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote: +Recommended properties: +- ranges: Allows valid translation between child's address space and + parent's. Must be present if the device has sub-nodes. +- #address-cells: Specifies the number of cells used to represent + physical base addresses. Must be present if the device has + sub-nodes and set to 1 if present +- #size-cells: Specifies the number of cells used to represent + the size of an address. Must be present if the device has + sub-nodes and set to 1 if present Why are we specifying #address-cells/#size-cells here? A: it has sub-nodes which have REG property, don't we need to specify #address-cells/#size-cells? If a node has a reg entry, its parent should have #size-cells and #address-cells to allow it to be parsed properly. Yes, but why do we need to specify in this binding how many cells there will be, especially since this binding only addresses the clock provider aspect of the clockgen nodes (e.g. it doesn't describe the reg)? Or rather, it's partially describing the non-clock aspect, and doesn't address the clock aspect at all AFAICT. First of all, they are not Required properties, they are optional. If present, we should give them a value of 1. Why does it matter, so long as the values translate properly? It's not as if you're defining a special reg format. It's not that big of a deal, but it seems unnecessary. Then, yes, this binding describes clockgen node which is CLOCK BLOCK. Sorry, I missed where reg was documented due to the required/recommended split. Where does the actual input clock frequency go? U-Boot puts it in the clockgen node itself as clock-frequency, but that isn't described in the binding. How does that relate to the sysclk node? If fsl,qoriq-sysclk- 1.0 is supposed to indicate that clock-frequency can be found in the parent node, that isn't specified by the binding, nor is clock-frequency shown in the example. clock-frequency is a wired property. Do you mean weird? It is in clockgen node right now. But it should be placed somewhere in clock nodes. If we were doing this from scratch, yes, but there's existing U-Boot code that we want to be compatible with. If I describe here, I would be asked why it is related to clockgen node? That's not a good reason to leave it undocumented. What is the difference between fsl,qoriq-sysclk-1.0 and fsl,qoriq- sysclk-2.0? How does the concept of a fixed input clock change? Technically, there is no difference between *sysclk-1.0 and *-2.0, just like Clockgen-2.0 and 1.0. Naming like this just to indicate they belong to chassis 2.0 and 1.0 respectively. I guess it's OK if it encourages people to consider switching to the standard fixed-clock for future chassis. So the only thing that really needs to be fixed is the missing clock-frequency documentation. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: 答复: [v7] clk: corenet: Adds the clock binding
Thanks for your review. I will send next version of patch. Thanks, Yuantian -Original Message- From: Wood Scott-B07421 Sent: 2014年1月10日 星期五 5:19 To: Tang Yuantian-B29983 Cc: Mark Rutland; ga...@kernel.crashing.org; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org Subject: Re: 答复: [v7] clk: corenet: Adds the clock binding On Wed, 2014-01-08 at 20:57 -0600, Tang Yuantian-B29983 wrote: Thanks for you review. See my response inline. Thanks, Yuantian -Original Message- From: Wood Scott-B07421 Sent: 2014年1月9日 星期四 2:44 To: Mark Rutland Cc: Tang Yuantian-B29983; ga...@kernel.crashing.org; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org Subject: Re: 答复: [v7] clk: corenet: Adds the clock binding On Wed, 2014-01-08 at 09:30 +, Mark Rutland wrote: On Wed, Jan 08, 2014 at 08:53:56AM +, Yuantian Tang wrote: 发件人: Wood Scott-B07421 发送时间: 2014年1月8日 8:21 收件人: Tang Yuantian-B29983 抄送: ga...@kernel.crashing.org; mark.rutl...@arm.com; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org 主题: Re: [v7] clk: corenet: Adds the clock binding On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote: +Recommended properties: +- ranges: Allows valid translation between child's address +space and + parent's. Must be present if the device has sub-nodes. +- #address-cells: Specifies the number of cells used to represent + physical base addresses. Must be present if the device has + sub-nodes and set to 1 if present +- #size-cells: Specifies the number of cells used to represent + the size of an address. Must be present if the device has + sub-nodes and set to 1 if present Why are we specifying #address-cells/#size-cells here? A: it has sub-nodes which have REG property, don't we need to specify #address-cells/#size-cells? If a node has a reg entry, its parent should have #size-cells and #address-cells to allow it to be parsed properly. Yes, but why do we need to specify in this binding how many cells there will be, especially since this binding only addresses the clock provider aspect of the clockgen nodes (e.g. it doesn't describe the reg)? Or rather, it's partially describing the non-clock aspect, and doesn't address the clock aspect at all AFAICT. First of all, they are not Required properties, they are optional. If present, we should give them a value of 1. Why does it matter, so long as the values translate properly? It's not as if you're defining a special reg format. It's not that big of a deal, but it seems unnecessary. Then, yes, this binding describes clockgen node which is CLOCK BLOCK. Sorry, I missed where reg was documented due to the required/recommended split. Where does the actual input clock frequency go? U-Boot puts it in the clockgen node itself as clock-frequency, but that isn't described in the binding. How does that relate to the sysclk node? If fsl,qoriq-sysclk- 1.0 is supposed to indicate that clock-frequency can be found in the parent node, that isn't specified by the binding, nor is clock-frequency shown in the example. clock-frequency is a wired property. Do you mean weird? It is in clockgen node right now. But it should be placed somewhere in clock nodes. If we were doing this from scratch, yes, but there's existing U-Boot code that we want to be compatible with. If I describe here, I would be asked why it is related to clockgen node? That's not a good reason to leave it undocumented. What is the difference between fsl,qoriq-sysclk-1.0 and fsl,qoriq- sysclk-2.0? How does the concept of a fixed input clock change? Technically, there is no difference between *sysclk-1.0 and *-2.0, just like Clockgen-2.0 and 1.0. Naming like this just to indicate they belong to chassis 2.0 and 1.0 respectively. I guess it's OK if it encourages people to consider switching to the standard fixed-clock for future chassis. So the only thing that really needs to be fixed is the missing clock- frequency documentation. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
答复: [v7] clk: corenet: Adds the clock binding
发件人: Wood Scott-B07421 发送时间: 2014年1月8日 8:21 收件人: Tang Yuantian-B29983 抄送: ga...@kernel.crashing.org; mark.rutl...@arm.com; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org 主题: Re: [v7] clk: corenet: Adds the clock binding On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote: +Recommended properties: +- ranges: Allows valid translation between child's address space and + parent's. Must be present if the device has sub-nodes. +- #address-cells: Specifies the number of cells used to represent + physical base addresses. Must be present if the device has + sub-nodes and set to 1 if present +- #size-cells: Specifies the number of cells used to represent + the size of an address. Must be present if the device has + sub-nodes and set to 1 if present Why are we specifying #address-cells/#size-cells here? A: it has sub-nodes which have REG property, don't we need to specify #address-cells/#size-cells? +2. Clock Provider/Consumer Binding + +Most of the bindings are from the common clock binding[1]. + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : Should include one of the following: + * fsl,qoriq-core-pll-1.0 for core PLL clocks (v1.0) +* fsl,qoriq-core-pll-2.0 for core PLL clocks (v2.0) +* fsl,qoriq-core-mux-1.0 for core mux clocks (v1.0) +* fsl,qoriq-core-mux-2.0 for core mux clocks (v2.0) + * fsl,qoriq-sysclk-1.0: for input system clock (v1.0) + * fsl,qoriq-sysclk-2.0: for input system clock (v2.0) Some of those lines use tabs and others spaces -- I can fix when applying. A: sorry for this and thanks for fixing. Regards, Yuantian -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: 答复: [v7] clk: corenet: Adds the clock binding
On Wed, Jan 08, 2014 at 08:53:56AM +, Yuantian Tang wrote: 发件人: Wood Scott-B07421 发送时间: 2014年1月8日 8:21 收件人: Tang Yuantian-B29983 抄送: ga...@kernel.crashing.org; mark.rutl...@arm.com; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org 主题: Re: [v7] clk: corenet: Adds the clock binding On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote: +Recommended properties: +- ranges: Allows valid translation between child's address space and + parent's. Must be present if the device has sub-nodes. +- #address-cells: Specifies the number of cells used to represent + physical base addresses. Must be present if the device has + sub-nodes and set to 1 if present +- #size-cells: Specifies the number of cells used to represent + the size of an address. Must be present if the device has + sub-nodes and set to 1 if present Why are we specifying #address-cells/#size-cells here? A: it has sub-nodes which have REG property, don't we need to specify #address-cells/#size-cells? If a node has a reg entry, its parent should have #size-cells and #address-cells to allow it to be parsed properly. Mark. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: 答复: [v7] clk: corenet: Adds the clock binding
Thanks for you review. See my response inline. Thanks, Yuantian -Original Message- From: Wood Scott-B07421 Sent: 2014年1月9日 星期四 2:44 To: Mark Rutland Cc: Tang Yuantian-B29983; ga...@kernel.crashing.org; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org Subject: Re: 答复: [v7] clk: corenet: Adds the clock binding On Wed, 2014-01-08 at 09:30 +, Mark Rutland wrote: On Wed, Jan 08, 2014 at 08:53:56AM +, Yuantian Tang wrote: 发件人: Wood Scott-B07421 发送时间: 2014年1月8日 8:21 收件人: Tang Yuantian-B29983 抄送: ga...@kernel.crashing.org; mark.rutl...@arm.com; devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org 主题: Re: [v7] clk: corenet: Adds the clock binding On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote: +Recommended properties: +- ranges: Allows valid translation between child's address space and + parent's. Must be present if the device has sub-nodes. +- #address-cells: Specifies the number of cells used to represent + physical base addresses. Must be present if the device has + sub-nodes and set to 1 if present +- #size-cells: Specifies the number of cells used to represent + the size of an address. Must be present if the device has + sub-nodes and set to 1 if present Why are we specifying #address-cells/#size-cells here? A: it has sub-nodes which have REG property, don't we need to specify #address-cells/#size-cells? If a node has a reg entry, its parent should have #size-cells and #address-cells to allow it to be parsed properly. Yes, but why do we need to specify in this binding how many cells there will be, especially since this binding only addresses the clock provider aspect of the clockgen nodes (e.g. it doesn't describe the reg)? Or rather, it's partially describing the non-clock aspect, and doesn't address the clock aspect at all AFAICT. First of all, they are not Required properties, they are optional. If present, we should give them a value of 1. Then, yes, this binding describes clockgen node which is CLOCK BLOCK. It should take care of its sub-nodes which are clock nodes to be parsed properly. Where does the actual input clock frequency go? U-Boot puts it in the clockgen node itself as clock-frequency, but that isn't described in the binding. How does that relate to the sysclk node? If fsl,qoriq-sysclk- 1.0 is supposed to indicate that clock-frequency can be found in the parent node, that isn't specified by the binding, nor is clock-frequency shown in the example. clock-frequency is a wired property. It is in clockgen node right now. But it should be placed somewhere in clock nodes. If I describe here, I would be asked why it is related to clockgen node? If you think showing it up is OK, I like to do it. What is the difference between fsl,qoriq-sysclk-1.0 and fsl,qoriq- sysclk-2.0? How does the concept of a fixed input clock change? Technically, there is no difference between *sysclk-1.0 and *-2.0, just like Clockgen-2.0 and 1.0. Naming like this just to indicate they belong to chassis 2.0 and 1.0 respectively. Regards, Yuantian -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v7] clk: corenet: Adds the clock binding
On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote: +Recommended properties: +- ranges: Allows valid translation between child's address space and + parent's. Must be present if the device has sub-nodes. +- #address-cells: Specifies the number of cells used to represent + physical base addresses. Must be present if the device has + sub-nodes and set to 1 if present +- #size-cells: Specifies the number of cells used to represent + the size of an address. Must be present if the device has + sub-nodes and set to 1 if present Why are we specifying #address-cells/#size-cells here? +2. Clock Provider/Consumer Binding + +Most of the bindings are from the common clock binding[1]. + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : Should include one of the following: + * fsl,qoriq-core-pll-1.0 for core PLL clocks (v1.0) +* fsl,qoriq-core-pll-2.0 for core PLL clocks (v2.0) +* fsl,qoriq-core-mux-1.0 for core mux clocks (v1.0) +* fsl,qoriq-core-mux-2.0 for core mux clocks (v2.0) + * fsl,qoriq-sysclk-1.0: for input system clock (v1.0) + * fsl,qoriq-sysclk-2.0: for input system clock (v2.0) Some of those lines use tabs and others spaces -- I can fix when applying. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v7] clk: corenet: Adds the clock binding
PING.
Thanks,
Yuantian
-Original Message-
From: Tang Yuantian-B29983
Sent: 2013年11月20日 星期三 17:05
To: ga...@kernel.crashing.org
Cc: devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
mark.rutl...@arm.com; Wood Scott-B07421; grant.lik...@secretlab.ca; Tang
Yuantian-B29983; Tang Yuantian-B29983; Li Yang-Leo-R58472
Subject: [PATCH v7] clk: corenet: Adds the clock binding
From: Tang Yuantian yuantian.t...@freescale.com
Adds the clock bindings for Freescale PowerPC CoreNet platforms
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
v7:
- refined some properties' definitions
v6:
- splited the previous patch into 2 parts, one is for binding(this
one),
the other is for DTS modification(will submit once this gets
accepted)
- fixed typo
- refined #clock-cells and clock-output-names properties
- removed fixed-clock compatible string
v5:
- refine the binding document
- update the compatible string
v4:
- add binding document
- update compatible string
- update the reg property
v3:
- fix typo
v2:
- add t4240, b4420, b4860 support
- remove pll/4 clock from p2041, p3041 and p5020 board
.../devicetree/bindings/clock/corenet-clock.txt| 128
+
1 file changed, 128 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/corenet-
clock.txt
diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt
b/Documentation/devicetree/bindings/clock/corenet-clock.txt
new file mode 100644
index 000..609ba2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
@@ -0,0 +1,128 @@
+* Clock Block on Freescale CoreNet Platforms
+
+Freescale CoreNet chips take primary clocking input from the external
+SYSCLK signal. The SYSCLK input (frequency) is multiplied using
+multiple phase locked loops (PLL) to create a variety of frequencies
+which can then be passed to a variety of internal logic, including
+cores and peripheral IP blocks.
+Please refer to the Reference Manual for details.
+
+1. Clock Block Binding
+
+Required properties:
+- compatible: Should contain a specific clock block compatible string
+ and a single chassis clock compatible string.
+ Clock block strings include, but not limited to, one of the:
+ * fsl,p2041-clockgen
+ * fsl,p3041-clockgen
+ * fsl,p4080-clockgen
+ * fsl,p5020-clockgen
+ * fsl,p5040-clockgen
+ * fsl,t4240-clockgen
+ * fsl,b4420-clockgen
+ * fsl,b4860-clockgen
+ Chassis clock strings include:
+ * fsl,qoriq-clockgen-1.0: for chassis 1.0 clocks
+ * fsl,qoriq-clockgen-2.0: for chassis 2.0 clocks
+- reg: Offset and length of the clock register set
+
+Recommended properties:
+- ranges: Allows valid translation between child's address space and
+ parent's. Must be present if the device has sub-nodes.
+- #address-cells: Specifies the number of cells used to represent
+ physical base addresses. Must be present if the device has
+ sub-nodes and set to 1 if present
+- #size-cells: Specifies the number of cells used to represent
+ the size of an address. Must be present if the device has
+ sub-nodes and set to 1 if present
+
+2. Clock Provider/Consumer Binding
+
+Most of the bindings are from the common clock binding[1].
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : Should include one of the following:
+ * fsl,qoriq-core-pll-1.0 for core PLL clocks (v1.0)
+* fsl,qoriq-core-pll-2.0 for core PLL clocks (v2.0)
+* fsl,qoriq-core-mux-1.0 for core mux clocks (v1.0)
+* fsl,qoriq-core-mux-2.0 for core mux clocks (v2.0)
+ * fsl,qoriq-sysclk-1.0: for input system clock (v1.0)
+ * fsl,qoriq-sysclk-2.0: for input system clock (v2.0)
+- #clock-cells: From common clock binding. The number of cells in a
+ clock-specifier. Should be 0 for fsl,qoriq-sysclk-[1,2].0
+ clocks, or 1 for fsl,qoriq-core-pll-[1,2].0 clocks.
+ For fsl,qoriq-core-pll-[1,2].0 clocks, the single
+ clock-specifier cell may take the following values:
+ * 0 - equal to the PLL frequency
+ * 1 - equal to the PLL frequency divided by 2
+ * 2 - equal to the PLL frequency divided by 4
+
+Recommended properties:
+- clocks: Should be the phandle of input parent clock
+- clock-names: From common clock binding, indicates the clock name
+- clock-output-names: From common clock binding, indicates the names of
+ output clocks
+- reg: Should be the offset and length of clock block base address.
+ The length should be 4.
+
+Example for clock block and clock provider:
+/ {
+ clockgen: global-utilities@e1000 {
+ compatible = fsl,p5020-clockgen, fsl,qoriq-clockgen-1.0;
+ ranges = 0x0 0xe1000 0x1000
RE: [PATCH v7] clk: corenet: Adds the clock binding
Hi Scott,
Do you have any comments about this patch? If not, please pick it up.
Thanks,
Yuantian
-Original Message-
From: Tang Yuantian-B29983
Sent: 2013年11月20日 星期三 17:05
To: ga...@kernel.crashing.org
Cc: devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
mark.rutl...@arm.com; Wood Scott-B07421; grant.lik...@secretlab.ca; Tang
Yuantian-B29983; Tang Yuantian-B29983; Li Yang-Leo-R58472
Subject: [PATCH v7] clk: corenet: Adds the clock binding
From: Tang Yuantian yuantian.t...@freescale.com
Adds the clock bindings for Freescale PowerPC CoreNet platforms
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
v7:
- refined some properties' definitions
v6:
- splited the previous patch into 2 parts, one is for binding(this
one),
the other is for DTS modification(will submit once this gets
accepted)
- fixed typo
- refined #clock-cells and clock-output-names properties
- removed fixed-clock compatible string
v5:
- refine the binding document
- update the compatible string
v4:
- add binding document
- update compatible string
- update the reg property
v3:
- fix typo
v2:
- add t4240, b4420, b4860 support
- remove pll/4 clock from p2041, p3041 and p5020 board
.../devicetree/bindings/clock/corenet-clock.txt| 128
+
1 file changed, 128 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/corenet-
clock.txt
diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt
b/Documentation/devicetree/bindings/clock/corenet-clock.txt
new file mode 100644
index 000..609ba2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
@@ -0,0 +1,128 @@
+* Clock Block on Freescale CoreNet Platforms
+
+Freescale CoreNet chips take primary clocking input from the external
+SYSCLK signal. The SYSCLK input (frequency) is multiplied using
+multiple phase locked loops (PLL) to create a variety of frequencies
+which can then be passed to a variety of internal logic, including
+cores and peripheral IP blocks.
+Please refer to the Reference Manual for details.
+
+1. Clock Block Binding
+
+Required properties:
+- compatible: Should contain a specific clock block compatible string
+ and a single chassis clock compatible string.
+ Clock block strings include, but not limited to, one of the:
+ * fsl,p2041-clockgen
+ * fsl,p3041-clockgen
+ * fsl,p4080-clockgen
+ * fsl,p5020-clockgen
+ * fsl,p5040-clockgen
+ * fsl,t4240-clockgen
+ * fsl,b4420-clockgen
+ * fsl,b4860-clockgen
+ Chassis clock strings include:
+ * fsl,qoriq-clockgen-1.0: for chassis 1.0 clocks
+ * fsl,qoriq-clockgen-2.0: for chassis 2.0 clocks
+- reg: Offset and length of the clock register set
+
+Recommended properties:
+- ranges: Allows valid translation between child's address space and
+ parent's. Must be present if the device has sub-nodes.
+- #address-cells: Specifies the number of cells used to represent
+ physical base addresses. Must be present if the device has
+ sub-nodes and set to 1 if present
+- #size-cells: Specifies the number of cells used to represent
+ the size of an address. Must be present if the device has
+ sub-nodes and set to 1 if present
+
+2. Clock Provider/Consumer Binding
+
+Most of the bindings are from the common clock binding[1].
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : Should include one of the following:
+ * fsl,qoriq-core-pll-1.0 for core PLL clocks (v1.0)
+* fsl,qoriq-core-pll-2.0 for core PLL clocks (v2.0)
+* fsl,qoriq-core-mux-1.0 for core mux clocks (v1.0)
+* fsl,qoriq-core-mux-2.0 for core mux clocks (v2.0)
+ * fsl,qoriq-sysclk-1.0: for input system clock (v1.0)
+ * fsl,qoriq-sysclk-2.0: for input system clock (v2.0)
+- #clock-cells: From common clock binding. The number of cells in a
+ clock-specifier. Should be 0 for fsl,qoriq-sysclk-[1,2].0
+ clocks, or 1 for fsl,qoriq-core-pll-[1,2].0 clocks.
+ For fsl,qoriq-core-pll-[1,2].0 clocks, the single
+ clock-specifier cell may take the following values:
+ * 0 - equal to the PLL frequency
+ * 1 - equal to the PLL frequency divided by 2
+ * 2 - equal to the PLL frequency divided by 4
+
+Recommended properties:
+- clocks: Should be the phandle of input parent clock
+- clock-names: From common clock binding, indicates the clock name
+- clock-output-names: From common clock binding, indicates the names of
+ output clocks
+- reg: Should be the offset and length of clock block base address.
+ The length should be 4.
+
+Example for clock block and clock provider:
+/ {
+ clockgen: global-utilities@e1000 {
+ compatible = fsl,p5020-clockgen, fsl
[PATCH v7] clk: corenet: Adds the clock binding
From: Tang Yuantian yuantian.t...@freescale.com
Adds the clock bindings for Freescale PowerPC CoreNet platforms
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
v7:
- refined some properties' definitions
v6:
- splited the previous patch into 2 parts, one is for binding(this one),
the other is for DTS modification(will submit once this gets accepted)
- fixed typo
- refined #clock-cells and clock-output-names properties
- removed fixed-clock compatible string
v5:
- refine the binding document
- update the compatible string
v4:
- add binding document
- update compatible string
- update the reg property
v3:
- fix typo
v2:
- add t4240, b4420, b4860 support
- remove pll/4 clock from p2041, p3041 and p5020 board
.../devicetree/bindings/clock/corenet-clock.txt| 128 +
1 file changed, 128 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/corenet-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt
b/Documentation/devicetree/bindings/clock/corenet-clock.txt
new file mode 100644
index 000..609ba2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
@@ -0,0 +1,128 @@
+* Clock Block on Freescale CoreNet Platforms
+
+Freescale CoreNet chips take primary clocking input from the external
+SYSCLK signal. The SYSCLK input (frequency) is multiplied using
+multiple phase locked loops (PLL) to create a variety of frequencies
+which can then be passed to a variety of internal logic, including
+cores and peripheral IP blocks.
+Please refer to the Reference Manual for details.
+
+1. Clock Block Binding
+
+Required properties:
+- compatible: Should contain a specific clock block compatible string
+ and a single chassis clock compatible string.
+ Clock block strings include, but not limited to, one of the:
+ * fsl,p2041-clockgen
+ * fsl,p3041-clockgen
+ * fsl,p4080-clockgen
+ * fsl,p5020-clockgen
+ * fsl,p5040-clockgen
+ * fsl,t4240-clockgen
+ * fsl,b4420-clockgen
+ * fsl,b4860-clockgen
+ Chassis clock strings include:
+ * fsl,qoriq-clockgen-1.0: for chassis 1.0 clocks
+ * fsl,qoriq-clockgen-2.0: for chassis 2.0 clocks
+- reg: Offset and length of the clock register set
+
+Recommended properties:
+- ranges: Allows valid translation between child's address space and
+ parent's. Must be present if the device has sub-nodes.
+- #address-cells: Specifies the number of cells used to represent
+ physical base addresses. Must be present if the device has
+ sub-nodes and set to 1 if present
+- #size-cells: Specifies the number of cells used to represent
+ the size of an address. Must be present if the device has
+ sub-nodes and set to 1 if present
+
+2. Clock Provider/Consumer Binding
+
+Most of the bindings are from the common clock binding[1].
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : Should include one of the following:
+ * fsl,qoriq-core-pll-1.0 for core PLL clocks (v1.0)
+* fsl,qoriq-core-pll-2.0 for core PLL clocks (v2.0)
+* fsl,qoriq-core-mux-1.0 for core mux clocks (v1.0)
+* fsl,qoriq-core-mux-2.0 for core mux clocks (v2.0)
+ * fsl,qoriq-sysclk-1.0: for input system clock (v1.0)
+ * fsl,qoriq-sysclk-2.0: for input system clock (v2.0)
+- #clock-cells: From common clock binding. The number of cells in a
+ clock-specifier. Should be 0 for fsl,qoriq-sysclk-[1,2].0
+ clocks, or 1 for fsl,qoriq-core-pll-[1,2].0 clocks.
+ For fsl,qoriq-core-pll-[1,2].0 clocks, the single
+ clock-specifier cell may take the following values:
+ * 0 - equal to the PLL frequency
+ * 1 - equal to the PLL frequency divided by 2
+ * 2 - equal to the PLL frequency divided by 4
+
+Recommended properties:
+- clocks: Should be the phandle of input parent clock
+- clock-names: From common clock binding, indicates the clock name
+- clock-output-names: From common clock binding, indicates the names of
+ output clocks
+- reg: Should be the offset and length of clock block base address.
+ The length should be 4.
+
+Example for clock block and clock provider:
+/ {
+ clockgen: global-utilities@e1000 {
+ compatible = fsl,p5020-clockgen, fsl,qoriq-clockgen-1.0;
+ ranges = 0x0 0xe1000 0x1000;
+ reg = 0xe1000 0x1000;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ sysclk: sysclk {
+ #clock-cells = 0;
+ compatible = fsl,qoriq-sysclk-1.0;
+ clock-output-names = sysclk;
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = 1;
+ reg = 0x800 0x4;
