Hi
While running LTP hugeltb tests on freescale powerpc board, I'm getting
[ 7253.637591] BUG: using smp_processor_id() in preemptible [ ]
code: hugemmap01/9048
[ 7253.637601] caller is free_hugepd_range.constprop.25+0x88/0x1a8
[ 7253.637605] CPU: 1 PID: 9048 Comm: hugemmap01
On 01/17/2014 05:23 PM, Nikita Yushchenko wrote:
Hi
While running LTP hugeltb tests on freescale powerpc board, I'm getting
[ 7253.637591] BUG: using smp_processor_id() in preemptible [ ]
code: hugemmap01/9048
[ 7253.637601] caller is free_hugepd_range.constprop.25+0x88/0x1a8
[
Could you try this?
powerpc/hugetlb: replace __get_cpu_var with get_cpu_var
Replace __get_cpu_var safely with get_cpu_var to avoid
the following call trace:
Confirmed, no more acktraces.
Nikita
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Hi Scott,
Thanks for you feedback.
On 01/17/2014 12:35 AM, Scott Wood wrote:
On Thu, 2014-01-16 at 14:38 +0100, Valentin Longchamp wrote:
This patch introduces the support for Keymile's kmp204x reference
design. This design is based on Freescale's P2040/P2041 SoC.
The peripherals used by
On Fri, 2014-01-17 at 12:27 +0530, Aneesh Kumar K.V wrote:
Li Zhong zh...@linux.vnet.ibm.com writes:
It seems that forward declaration couldn't work well with typedef, use
struct spinlock directly to avoiding following build errors:
In file included from include/linux/spinlock.h:81,
Commit 5091f0c (powerpc/pseries: Fix PCIE link speed endian issue)
introduced a regression on the PCI link speed detection using the
device-tree property. The ibm,pcie-link-speed-stats property is composed
of two 32-bit integers, the first one being the maxinum link speed and
the second the
These two patches fix problems on the PCI-E link speed detection.
The first one fixes a regression and adds some improvements on the
code, and the second one adds definitions for Gen3 speeds.
Kleber Sacilotto de Souza (2):
powerpc/pseries: fix regression on PCI link speed
powerpc/pseries: add
Rev3 of the PCI Express Base Specification defines a Supported Link
Speeds Vector where the bit definitions within this field are:
Bit 0 - 2.5 GT/s
Bit 1 - 5.0 GT/s
Bit 2 - 8.0 GT/s
This vector definition is used by the platform firmware to export the
maximum and current link speeds of the PCI
On Jan 17, 2014, at 12:09 AM, Prabhakar Kushwaha prabha...@freescale.com
wrote:
Currently IFC NAND driver is enabled in corenet32smp_defconfig. But IFC
controller is not enabled
So, Enable IFC controller in corenet32smp_defconfig.
Signed-off-by: Prabhakar Kushwaha
On Jan 16, 2014, at 2:14 AM, Minghuan Lian minghuan.l...@freescale.com wrote:
For PEXCSRBAR, bit 3-0 indicate prefetchable and address type.
So when getting base address, these bits should be masked,
otherwise we may get incorrect base address.
Signed-off-by: Minghuan Lian
On Jan 15, 2014, at 11:42 PM, Prabhakar Kushwaha prabha...@freescale.com
wrote:
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file includes.
Also remove
Hi All,
First, let me introduce myself. My name is Christian Zigotzky. I'm 39
years old and I live in Germany. My hobbies are traveling and computing.
I'm a member of the A-EON Core Linux Support Team.
A-EON Technology, in co-operation with Varisys, Hyperion Entertainment
and AmigaKit
Hi All,
First, let me introduce myself. My name is Christian Zigotzky. I'm 39
years old and I live in Germany. My hobbies are traveling and computing.
I'm a member of the A-EON Core Linux Support Team.
A-EON Technology, in co-operation with Varisys, Hyperion Entertainment
and AmigaKit
On Fri, 2014-01-17 at 11:02 -0600, Kumar Gala wrote:
On Jan 17, 2014, at 12:09 AM, Prabhakar Kushwaha prabha...@freescale.com
wrote:
Currently IFC NAND driver is enabled in corenet32smp_defconfig. But IFC
controller is not enabled
So, Enable IFC controller in corenet32smp_defconfig.
On Fri, 2014-01-17 at 21:30 +0800, Li Zhong wrote:
On Fri, 2014-01-17 at 12:27 +0530, Aneesh Kumar K.V wrote:
Li Zhong zh...@linux.vnet.ibm.com writes:
It seems that forward declaration couldn't work well with typedef, use
struct spinlock directly to avoiding following build errors:
On Fri, 2014-01-17 at 13:51 +0100, Valentin Longchamp wrote:
Hi Scott,
Thanks for you feedback.
On 01/17/2014 12:35 AM, Scott Wood wrote:
On Thu, 2014-01-16 at 14:38 +0100, Valentin Longchamp wrote:
This patch introduces the support for Keymile's kmp204x reference
design. This design
On Thu, 2014-01-16 at 18:02 +0800, Shengzhou Liu wrote:
+ cpc: l3-cache-controller@1 {
+ compatible = cache;
+ reg = 0x1 0x1000
+0x11000 0x1000
+0x12000 0x1000;
+ interrupts = 16 2 1 27
+
On Wed, 2014-01-15 at 14:54 +1100, Benjamin Herrenschmidt wrote:
On Fri, 2014-01-10 at 18:44 -0600, Scott Wood wrote:
Highlights include 32-bit booke relocatable support, e6500 hardware
tablewalk support, various e500 SPE fixes, some new/revived boards, and
e6500 deeper idle and altivec
...and make CONFIG_PPC_FSL_BOOK3E conflict with CONFIG_PPC_64K_PAGES.
This fixes a build break with CONFIG_PPC_64K_PAGES on 64-bit book3e,
that was introduced by commit 28efc35fe68dacbddc4b12c2fa8f2df1593a4ad3
(powerpc/e6500: TLB miss handler with hardware tablewalk support).
Signed-off-by:
On Mon, 2014-01-13 at 16:16 +0800, Tang Yuantian wrote:
+Example for clock block and clock provider:
+/ {
+ clockgen: global-utilities@e1000 {
+ compatible = fsl,p5020-clockgen, fsl,qoriq-clockgen-1.0;
+ ranges = 0x0 0xe1000 0x1000;
+ clock-frequency =
This contains a fix for a chroma_defconfig build break that was
introduced by e6500 tablewalk support, and a device tree binding patch
that missed the previous pull request due to some last-minute polishing.
The following changes since commit fac515db45207718168cb55ca4d0a390e43b61af:
Merge
This patch provides error logging interfaces to report critical
powernv error logs to FSP.
All the required information to dump the error is collected
at POWERNV level through error log interfaces
and then pushed on to FSP.
Signed-off-by: Deepthi Dharwar deep...@linux.vnet.ibm.com
---
This patch series defines generic interfaces for error logging to
push down critical errors from powernv platform to FSP.
Also, it contains few minor fixes for the exisiting error logging
framework that retrieves error logs from FSP.
This patch only adds the framework to log errors. Coming days
Correct spell error in opal-elog.c
Signed-off-by: Deepthi Dharwar deep...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/opal-elog.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/opal-elog.c
Currently some errors/info to be reported use
printk and the rest pr_fmt(). This patch
makes the complete error/event logging uniform.
Signed-off-by: Deepthi Dharwar deep...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/opal-elog.c | 14 ++
1 file changed, 6 insertions(+),
On 1/18/2014 12:19 AM, Scott Wood wrote:
On Fri, 2014-01-17 at 11:02 -0600, Kumar Gala wrote:
On Jan 17, 2014, at 12:09 AM, Prabhakar Kushwaha prabha...@freescale.com
wrote:
Currently IFC NAND driver is enabled in corenet32smp_defconfig. But IFC
controller is not enabled
So, Enable IFC
On 1/17/2014 10:38 PM, Kumar Gala wrote:
On Jan 15, 2014, at 11:42 PM, Prabhakar Kushwaha prabha...@freescale.com
wrote:
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file includes.
Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall() to make sure
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