* Jeremy Kerr j...@ozlabs.org [2014-02-11 14:05:17]:
Current ppc64_defconfig fails with:
arch/powerpc/platforms/cell/spufs/sched.c:86:0: error: MAX_USER_PRIO
redefined [-Werror]
cc1: all warnings being treated as errors
6b6350f1 introduced a generic MAX_USER_PRIO macro to
Hi Vaidy,
On 02/11/2014 12:32 PM, Vaidyanathan Srinivasan wrote:
From: Srivatsa S. Bhat srivatsa.b...@linux.vnet.ibm.com
On POWER systems, the CPU frequency is controlled at a core-level and
hence we need to serialize so that only one of the threads in the core
switches the core's frequency
Hi Vaidy,
On 02/11/2014 12:32 PM, Vaidyanathan Srinivasan wrote:
Backend driver to dynamically set voltage and frequency on
IBM POWER non-virtualized platforms. Power management SPRs
are used to set the required PState.
This driver works in conjunction with cpufreq governors
like
On Tue, Feb 11, 2014 at 03:24:17AM +0800, kbuild test robot wrote:
arch/powerpc/platforms/cell/spufs/sched.c:86:0: warning: MAX_USER_PRIO
redefined [enabled by default]
#define MAX_USER_PRIO (MAX_PRIO - MAX_RT_PRIO)
^
In file included from include/linux/sched.h:6:0,
On 02/07/2014 09:06 AM, Preeti U Murthy wrote:
From: Thomas Gleixner t...@linutronix.de
On some architectures, in certain CPU deep idle states the local timers stop.
An external clock device is used to wakeup these CPUs. The kernel support for
the
wakeup of these CPUs is provided by the tick
On Fri, Feb 7, 2014 at 10:28 PM, Torsten Duwe d...@lst.de wrote:
Ticket locks for ppc, version 2. Changes since v1:
* The atomically exchanged entity is always 32 bits.
* asm inline string variations thus removed.
* Carry the additional holder hint only #if defined(CONFIG_PPC_SPLPAR)
On Mon, Feb 10, 2014 at 8:40 AM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Fri, 2014-02-07 at 17:58 +0100, Torsten Duwe wrote:
typedef struct {
- volatile unsigned int slock;
-} arch_spinlock_t;
+ union {
+ __ticketpair_t head_tail;
+
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We will use this later to set the _PAGE_NUMA bit.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/hugetlb.h | 2 +-
arch/powerpc/include/asm/pgtable-ppc64.h | 26 +++---
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
So move it within the if loop
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
mm/mprotect.c | 21 +++--
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/mm/mprotect.c b/mm/mprotect.c
index
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Archs like ppc64 doesn't do tlb flush in set_pte/pmd functions. ppc64 also
doesn't implement
flush_tlb_range. ppc64 require the tlb flushing to be batched within ptl locks.
The reason
to do that is to ensure that the hash page table is in
Hello,
This patch series fix random application crashes observed on ppc64 with numa
balancing enabled. Without the patch we see crashes like
anacron[14551]: unhandled signal 11 at 0041 nip 3cfd54b4 lr
3cfd5464 code 30001
anacron[14599]: unhandled signal 11 at
On Tue, Feb 11, 2014 at 03:23:51PM +0530, Raghavendra KT wrote:
How much important to have holder information for PPC? From my
previous experiment
on x86, it was lock-waiter preemption which is problematic rather than
lock-holder preemption.
It's something very special to IBM pSeries: the
This series adds support for Keymile's COGE4 board, called kmcoge4. This
board is the reference design for further designs at Keymile around the
P2040/P2041 SoCs from Freescale. This reference design is internally
called kmp204x.
Changes in v2:
- add a patch so that the Zarlink vendor prefix is
Even though the company belongs to Microsemi, many chips are still
labeled as Zarlink. Among them is the family of network clock generators,
the zl3034x.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
Changes in v2:
- add a patch so that the Zarlink vendor prefix is
This patch introduces the support for Keymile's kmcoge4 board which is
the internal reference design for boards based on Freescale's
P2040/P2041 SoCs. This internal reference design is named kmp204x.
The peripherals used on this board are:
- SPI NOR Flash as bootloader medium
- NAND Flash with a
On 02/11/2014 05:34 AM, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
So move it within the if loop
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Reviewed-by: Rik van Riel r...@redhat.com
--
All rights reversed
On 02/11/2014 05:34 AM, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Archs like ppc64 doesn't do tlb flush in set_pte/pmd functions. ppc64 also
doesn't implement
flush_tlb_range. ppc64 require the tlb flushing to be batched within ptl
locks. The reason
On 02/11/2014 05:34 AM, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We will use this later to set the _PAGE_NUMA bit.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Acked-by: Rik van Riel r...@redhat.com
--
All rights reversed
On Tue, 11 Feb 2014, Daniel Lezcano wrote:
On 02/07/2014 09:06 AM, Preeti U Murthy wrote:
Setting the smp affinity on the earliest timer should be handled automatically
with the CLOCK_EVT_FEAT_DYNIRQ flag. Did you look at using this flag ?
How should this flag help? Not at all, because the
Hi Daniel,
Thank you very much for the review.
On 02/11/2014 03:46 PM, Daniel Lezcano wrote:
On 02/07/2014 09:06 AM, Preeti U Murthy wrote:
From: Thomas Gleixner t...@linutronix.de
On some architectures, in certain CPU deep idle states the local
timers stop.
An external clock device is
On Tue, Feb 11, 2014 at 04:04:54PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
So move it within the if loop
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Acked-by: Mel Gorman mgor...@suse.de
--
Mel Gorman
SUSE Labs
On Tue, Feb 11, 2014 at 04:04:55PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Archs like ppc64 doesn't do tlb flush in set_pte/pmd functions. ppc64 also
doesn't implement
flush_tlb_range. ppc64 require the tlb flushing to be batched within ptl
On Tue, Feb 11, 2014 at 04:04:53PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We will use this later to set the _PAGE_NUMA bit.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Acked-by: Mel Gorman mgor...@suse.de
--
Mel Gorman
On Fri, Feb 07, 2014 at 07:21:57PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace:
[c00736103c40]
On Tue, 2014-02-11 at 11:40 +0100, Torsten Duwe wrote:
On Tue, Feb 11, 2014 at 03:23:51PM +0530, Raghavendra KT wrote:
How much important to have holder information for PPC? From my
previous experiment
on x86, it was lock-waiter preemption which is problematic rather than
lock-holder
On Mon, 10 Feb 2014, Joonsoo Kim wrote:
On Fri, Feb 07, 2014 at 12:51:07PM -0600, Christoph Lameter wrote:
Here is a draft of a patch to make this work with memoryless nodes.
The first thing is that we modify node_match to also match if we hit an
empty node. In that case we simply take
On Tue, 2014-02-11 at 17:07 +, Mel Gorman wrote:
On Tue, Feb 11, 2014 at 04:04:55PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Archs like ppc64 doesn't do tlb flush in set_pte/pmd functions. ppc64 also
doesn't implement
flush_tlb_range.
On Tue, 2014-02-11 at 09:31 -0800, Greg KH wrote:
On Fri, Feb 07, 2014 at 07:21:57PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac]
On Tue, 2014-02-11 at 12:30 -0600, Scott Wood wrote:
It's something very special to IBM pSeries: the hypervisor can assign
fractions of physical CPUs to guests. Sometimes a guest with 4 quarter
CPUs will be faster than 1 monoprocessor. (correct me if I'm wrong).
The directed yield
I have been trial booting a 3.14-rc2 kernel for a 85xx platform
(dtbImage).
After mounting the root filesystem there are no messages from the init
scripts
and the serial console is not available for login.
In the kernel log messages there is:
of_serial f1004500.serial: Unknown serial port
On 02/11/2014 04:58 PM, Thomas Gleixner wrote:
On Tue, 11 Feb 2014, Daniel Lezcano wrote:
On 02/07/2014 09:06 AM, Preeti U Murthy wrote:
Setting the smp affinity on the earliest timer should be handled automatically
with the CLOCK_EVT_FEAT_DYNIRQ flag. Did you look at using this flag ?
How
On 02/11/2014 05:09 PM, Preeti U Murthy wrote:
Hi Daniel,
Thank you very much for the review.
On 02/11/2014 03:46 PM, Daniel Lezcano wrote:
On 02/07/2014 09:06 AM, Preeti U Murthy wrote:
From: Thomas Gleixner t...@linutronix.de
On some architectures, in certain CPU deep idle states the
On Feb 11, 2014, at 2:57 PM, Stephen N Chivers schiv...@csc.com.au wrote:
I have been trial booting a 3.14-rc2 kernel for a 85xx platform
(dtbImage).
After mounting the root filesystem there are no messages from the init
scripts
and the serial console is not available for login.
In
On 02/11/2014 11:33 PM, Kumar Gala wrote:
On Feb 11, 2014, at 2:57 PM, Stephen N Chivers schiv...@csc.com.au wrote:
I have been trial booting a 3.14-rc2 kernel for a 85xx platform
(dtbImage).
After mounting the root filesystem there are no messages from the init
scripts
and the serial
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote on
02/12/2014 09:51:43 AM:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
To: Kumar Gala ga...@kernel.crashing.org, Stephen N Chivers
schiv...@csc.com.au
Cc: linuxppc-dev@lists.ozlabs.org, Chris Proctor
On Tue, 2014-02-11 at 23:51 +0100, Sebastian Hesselbarth wrote:
On 02/11/2014 11:33 PM, Kumar Gala wrote:
Hmm,
Wondering if this caused the issue:
commit 105353145eafb3ea919f5cdeb652a9d8f270228e
Author: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Date: Tue Dec 3 14:52:00
On 02/12/2014 12:38 AM, Stephen N Chivers wrote:
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote on
On 02/11/2014 11:33 PM, Kumar Gala wrote:
On Feb 11, 2014, at 2:57 PM, Stephen N Chivers schiv...@csc.com.au wrote:
I have been trial booting a 3.14-rc2 kernel for a 85xx platform
On 02/12/2014 12:41 AM, Scott Wood wrote:
On Tue, 2014-02-11 at 23:51 +0100, Sebastian Hesselbarth wrote:
On 02/11/2014 11:33 PM, Kumar Gala wrote:
Hmm,
Wondering if this caused the issue:
commit 105353145eafb3ea919f5cdeb652a9d8f270228e
Author: Sebastian Hesselbarth
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote on
02/12/2014 10:46:36 AM:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
To: Scott Wood scottw...@freescale.com
Cc: Kumar Gala ga...@kernel.crashing.org, Stephen N Chivers
schiv...@csc.com.au, Chris Proctor
Greg KH gre...@linuxfoundation.org writes:
On Fri, Feb 07, 2014 at 07:21:57PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac]
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Tue, 2014-02-11 at 09:31 -0800, Greg KH wrote:
On Fri, Feb 07, 2014 at 07:21:57PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4]
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We will use this later to set the _PAGE_NUMA bit.
Acked-by: Mel Gorman mgor...@suse.de
Acked-by: Rik van Riel r...@redhat.com
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/hugetlb.h | 2
Hello,
This patch series fix random application crashes observed on ppc64 with numa
balancing enabled. Without the patch we see crashes like
anacron[14551]: unhandled signal 11 at 0041 nip 3cfd54b4 lr
3cfd5464 code 30001
anacron[14599]: unhandled signal 11 at
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
So move it within the if loop
Acked-by: Mel Gorman mgor...@suse.de
Reviewed-by: Rik van Riel r...@redhat.com
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
mm/mprotect.c | 21 +++--
1 file changed, 7
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Archs like ppc64 doesn't do tlb flush in set_pte/pmd functions. ppc64 also
doesn't implement
flush_tlb_range. ppc64 require the tlb flushing to be batched within ptl locks.
The reason
to do that is to ensure that the hash page table is in
Hi Linus !
Here is some powerpc goodness for -rc2. Arguably -rc1 material more than
-rc2 but I was travelling (again !)
It's mostly bug fixes including regressions, but there are a couple of
new things that I decided to drop-in.
One is a straightforward patch from Michael to add a bunch of P8
Hi all,
On Tue, 10 Dec 2013 10:26:10 +1100 Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Tue, 2013-12-10 at 10:10 +1100, Stephen Rothwell wrote:
Reported-by: Stephen Rothwell s...@canb.auug.org.au
Tested-by: Stephen Rothwell s...@canb.auug.org.au
Works for me. Thanks. I
On Wed, Feb 12, 2014 at 10:21:58AM +1000, Stephen N Chivers wrote:
But, the Interrupt Controller (MPIC)
goes AWOL and it is down hill from there.
The MPIC is specified in the DTS as:
mpic: pic@4 {
interrupt-controller;
On Wed, Jan 22, 2014 at 08:48:48AM +1100, Benjamin Herrenschmidt wrote:
It will be merged when I come back from vacation. It was too late for
3.13 so I'll send it to Linus next week and will CC -stable.
Hi Ben,
Any reason why this is still not merged yet?
Thanks,
Kevin
Cheers,
Ben.
perf is failing to resolve symbols in the VDSO. A while (1)
gettimeofday() loop shows:
93.99% [vdso] [.] 0x05e0
3.12% test[.] 0037.plt_call.gettimeofday@@GLIBC_2.18
2.81% test[.] main
The reason for this is that we are linking our VDSO shared libraries
at 1MB,
We are seeing a lot of hits in the VDSO that are not resolved by perf.
A while(1) gettimeofday() loop shows the issue:
27.64% [vdso] [.] 0x060c
22.57% [vdso] [.] 0x0628
16.88% [vdso] [.] 0x0610
The patch cleans up variable eeh_subsystem_enabled so that we needn't
refer the variable directly from external. Instead, we will use
function eeh_enabled() and eeh_set_enable() to operate the variable.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/eeh.h
When doing reset in order to recover the affected PE, we issue
hot reset on PE primary bus if it's not root bus. Otherwise, we
issue hot or fundamental reset on root port or PHB accordingly.
For the later case, we didn't cover the situation where PE only
includes root port and it potentially
We possiblly detect EEH errors during reboot, particularly in kexec
path, but it's impossible for device drivers and EEH core to handle
or recover them properly.
The patch registers one reboot notifier for EEH and disable EEH
subsystem during reboot. That means the EEH errors is going to be
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