Hi Varka,
Regarding a point you suggested.
On Fri, Jul 25, 2014 at 09:54:43AM +0530, Varka Bhadram wrote:
On 07/25/2014 09:33 AM, Nicolin Chen wrote:
(...)
+
+static const struct platform_device_id fsl_asrc_devtype[] = {
+{
+.name = imx35-asrc,
+
Hi Nicolin,
On 07/25/2014 11:24 AM, Nicolin Chen wrote:
Hi Varka,
Regarding a point you suggested.
On Fri, Jul 25, 2014 at 09:54:43AM +0530, Varka Bhadram wrote:
On 07/25/2014 09:33 AM, Nicolin Chen wrote:
(...)
+
+static const struct platform_device_id fsl_asrc_devtype[] = {
+ {
On Fri, Jul 25, 2014 at 11:47:42AM +0530, Varka Bhadram wrote:
Hi Nicolin,
On 07/25/2014 11:24 AM, Nicolin Chen wrote:
Hi Varka,
Regarding a point you suggested.
On Fri, Jul 25, 2014 at 09:54:43AM +0530, Varka Bhadram wrote:
On 07/25/2014 09:33 AM, Nicolin Chen wrote:
(...)
+
This series of patches add Freescale ASRC module driver support along
with the extra request in imx-sdma structure required by SDMA Device
to Device script.
The previous version has been in the maillist for nearly six months
without any comment and reply. So I decide to drop the SDMA part's
SDMA supports device to device (per_2_per) scripts to handle DMA transfering
between two peripheral devices. The per_2_per script, however, needs two dma
requests from two sides while the current structure only defined one request.
So this patch just simply adds the secondary request so as to let
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a different
output clock. The driver currently works as a Front End of DPCM with other Back
Ends DAI links such as ESAI-CS42888 and SSI-WM8962 and SAI.
On 07/25/2014 12:49 PM, Nicolin Chen wrote:
(...)
+
+ div[IN] = clk_get_rate(clk) / inrate;
+ if (div[IN] == 0) {
+ pair_err(failed to support input sample rate %dHz by asrck_%x,
+ inrate, clk_index[ideal ? OUT : IN]);
Oh... missed
Hi Varka,
Thank you for the comments!
On Fri, Jul 25, 2014 at 01:05:05PM +0530, Varka Bhadram wrote:
On 07/25/2014 12:49 PM, Nicolin Chen wrote:
(...)
+static const struct platform_device_id fsl_asrc_devtype[] = {
+{
+.name = imx35-asrc,
+.driver_data =
This series of patches add Freescale ASRC module driver support along
with the extra request in imx-sdma structure required by SDMA Device
to Device script.
The previous version has been in the maillist for nearly six months
without any comment and reply. So I decide to drop the SDMA part's
SDMA supports device to device (per_2_per) scripts to handle DMA transfering
between two peripheral devices. The per_2_per script, however, needs two dma
requests from two sides while the current structure only defined one request.
So this patch just simply adds the secondary request so as to let
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a different
output clock. The driver currently works as a Front End of DPCM with other Back
Ends DAI links such as ESAI-CS42888 and SSI-WM8962 and SAI.
On 07/25/2014 01:27 PM, Nicolin Chen wrote:
Hi Varka,
Thank you for the comments!
On Fri, Jul 25, 2014 at 01:05:05PM +0530, Varka Bhadram wrote:
On 07/25/2014 12:49 PM, Nicolin Chen wrote:
(...)
+static const struct platform_device_id fsl_asrc_devtype[] = {
+ {
+ .name =
On Fri, Jul 25, 2014 at 02:13:10PM +0530, Varka Bhadram wrote:
On 07/25/2014 01:27 PM, Nicolin Chen wrote:
+ if (IS_ERR(asrc_priv-regmap)) {
+ dev_err(pdev-dev, failed to init regmap\n);
+ return PTR_ERR(asrc_priv-regmap);
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if
On 07/25/2014 02:16 PM, Nicolin Chen wrote:
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a different
output clock. The driver currently works as a Front End of DPCM with other Back
Ends DAI links
Hi Varka,
On Fri, Jul 25, 2014 at 05:04:11PM +0530, Varka Bhadram wrote:
On 07/25/2014 02:16 PM, Nicolin Chen wrote:
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a
different
output clock.
On 07/25/2014 04:58 PM, Nicolin Chen wrote:
Hi Varka,
On Fri, Jul 25, 2014 at 05:04:11PM +0530, Varka Bhadram wrote:
On 07/25/2014 02:16 PM, Nicolin Chen wrote:
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal
On Wed, Jun 25, 2014 at 02:52:57PM +0400, Alexander Popov wrote:
This patch series introduces a device tree binding document for
the MPC512x DMA controller and adds device tree based DMA channel lookup
for it.
This version contains the improved device tree binding document:
#dma-cells is
The code selecting a device for the sdhci host has been
continuously tweaked (4b711cb13843f5082e82970dd1e8031383134a65
mmc: sdhci-pltfm: Add structure for host-specific data and
a4d2177f00a5252d825236c5124bc1e9918bdb41 mmc: sdhci-pltfm: dt
device does not pass parent to sdhci_alloc_host) while
From: Sudeep Holla sudeep.ho...@arm.com
This series adds a generic cacheinfo support similar to topology. The
implementation is based on x86 cacheinfo support. Currently x86, powerpc,
ia64 and s390 have their own implementations. While adding similar support
to ARM and ARM64, here is the attempt
From: Sudeep Holla sudeep.ho...@arm.com
This patch removes the redundant sysfs cacheinfo code by making use of
the newly introduced generic cacheinfo infrastructure.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras
The function rtas_flash_firmware passes the address of a data structure,
flash_block_list, when making the update-flash-64-and-reboot rtas call.
While the endianness of the address is handled correctly, the endianness
of the data is not. This patch ensures that the data in flash_block_list
is big
On Wed, Jul 23, 2014 at 07:23:37PM +0800, Nicolin Chen wrote:
The series of patches focus on issue fix inside fsl_sai_trigger().
Applied all, thanks.
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On Thu, 2014-07-24 at 22:11 -0500, Xie Shaohui-B21989 wrote:
Hello, Scott, Shruti,
There are two types MDIO controllers, each MAC has a corresponding MDIO
controller to access internal PHYs inside Serdes, another is dedicated
MDIO controller to access external PHYs (PHYs on board or riser
Hello Shao-Hui,
On 07/24/2014 10:11 PM, Shaohui Xie wrote:
Hello, Scott, Shruti,
There are two types MDIO controllers, each MAC has a corresponding
MDIO controller to access internal PHYs inside Serdes, another is
dedicated MDIO controller to access external PHYs (PHYs on board or
riser
On Thu, 2014-07-24 at 04:16 -0500, Caraman Mihai Claudiu-B02008 wrote:
Scott, Alex's request to define SPE handlers only for e500v2 implies changes
in 32-bit FSL kernel to have exclusive configurations for e200/e500v2 and
e500mc/e5500. We would probably need something like this, what's your
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