Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only)
bit.
This patch implements the handling of a _PAGE_RO flag to be used in place of
_PAGE_RW
Patchset:
1) powerpc32: adds handling of _PAGE_RO
2) powerpc/8xx: use _PAGE_RO instead of _PAGE_RW
All changes have been
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
v2 is a complete rework compared to v1
arch/powerpc/include/asm/pte-8xx.h | 7
Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only)
bit.
This patch implements the handling of a _PAGE_RO flag to be used in place of
_PAGE_RW
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
v2 is a complete rework compared to v1
On 17.12.14 04:44, Anton Blanchard wrote:
Hi Alex,
Git bisect managed to point me to this commit as the offender for
OOPSes on e5500 and e6500 (and maybe the G4 as well, not sure).
Doing a git revert of this commit on top of linus/master makes things
work fine for me again.
Ouch,
On Wednesday 17 December 2014 11:52:36 Benjamin Herrenschmidt wrote:
On Tue, 2014-12-16 at 18:47 +0200, Michael S. Tsirkin wrote:
On Sun, Dec 14, 2014 at 06:52:51PM +0200, Michael S. Tsirkin wrote:
virtio wants to read bitwise types from userspace using get_user. At the
moment this
On Wed, 2014-12-17 at 11:53 +0100, Arnd Bergmann wrote:
On Wednesday 17 December 2014 11:52:36 Benjamin Herrenschmidt wrote:
On Tue, 2014-12-16 at 18:47 +0200, Michael S. Tsirkin wrote:
On Sun, Dec 14, 2014 at 06:52:51PM +0200, Michael S. Tsirkin wrote:
virtio wants to read bitwise types
In the Makefile, string.o (which is generated from string.S) is
included into the list of objects being built unconditionally
(obj-y) in line 12.
Additionally, if CONFIG_PPC64 is set, it is included again in
line 17.
This patch removes the latter unnecessary inclusion.
Signed-off-by: Andreas
On 07.12.14 23:29, Rickard Strandqvist wrote:
Remove the function inst_set_field() that is not used anywhere.
This was partially found by using a static code analysis program called
cppcheck.
Signed-off-by: Rickard Strandqvist rickard_strandqv...@spectrumdigital.se
Thanks, applied all
On 03.12.14 04:48, Paul Mackerras wrote:
When a secondary hardware thread has finished running a KVM guest, we
currently put that thread into nap mode using a nap instruction in
the KVM code. This changes the code so that instead of doing a nap
instruction directly, we instead cause the
My configuration:
-
Host: Freescale i.MX512 with ARM Cortex A8 (USB 2.0 host controller)
Linux
kernel: 2.6.31, using EHCI USB driver
Hub: 4-PORT USB 1.1 HUB (Texas Instruments PN: tusb2046b)
Devices: 4 USB 1.1 audio codecs (Texas Instruments PN: pcm2901)
Note: each
The goal behind this patch is to be able to write userland tests for the
VPHN parsing code.
Suggested-by: Michael Ellerman m...@ellerman.id.au
Signed-off-by: Greg Kurz gk...@linux.vnet.ibm.com
---
arch/powerpc/mm/Makefile |1 +
arch/powerpc/mm/numa.c | 61
Hi,
This series addresses remarks from Ben and Michael (see individual patches).
The most notable changes are:
- the parsing code being pull out into a separate file in patch 3/4. This
allows to write userland tests like the one below.
- a full rewrite of the parsing logic in patch 4/4
--
The number of values returned by the H_HOME_NODE_ASSOCIATIVITY h_call deserves
to be explicitly defined, for a better understanding of the code.
Signed-off-by: Greg Kurz gk...@linux.vnet.ibm.com
---
No changes in v2.
arch/powerpc/mm/numa.c |8 ++--
1 file changed, 6 insertions(+), 2
The current VPHN parsing logic has some flaws that this patch aims to fix:
1) when the value 0x is read, the value 0x gets added to the
the output list and its element count isn't incremented. This is wrong.
According to PAPR+ the domain identifiers are packed into a sequence
On Mon, 15 Dec 2014, Michael Tessier wrote:
Hi,
I am dealing with a USB EHCI driver bug. Here is the info:
My configuration:
-
Host: Freescale i.MX512 with ARM Cortex A8 (USB 2.0 host controller)
Linux kernel: 2.6.31, using EHCI USB driver
As mentioned by other
The first argument to vphn_unpack_associativity() is a const long *, but the
parsing code expects __be64 values actually. Let's move the endian fixing
down for consistency.
Signed-off-by: Greg Kurz gk...@linux.vnet.ibm.com
---
v2: only move the endian fixing. The logic is reworked in another
On 12/17/2014 05:33 AM, Michael Ellerman wrote:
On Tue, 2014-12-16 at 23:35 +0530, Hari Bathini wrote:
With minor checks, we can move most of the code for nvram
under pseries to a common place to be re-used by other
powerpc platforms like powernv. This patch moves such
common code to
Commit 746c9e9f92dd of/base: Fix PowerPC address parsing hack limited
the applicability of the workaround whereby a missing ranges is treated
as an empty ranges. This workaround was hiding a bug in the etsec2
device tree nodes, which have children with reg, but did not have
ranges.
On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote:
Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read
Only) bit.
This patch implements the handling of a _PAGE_RO flag to be used in place of
_PAGE_RW
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote:
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
v2 is a complete
David Laight david.lai...@aculab.com writes:
From: Madhavan Srinivasan [mailto:ma...@linux.vnet.ibm.com]
...
I also wonder if it is possible to inspect the interrupted
code to determine the start/end of the RAS block.
(Easiest if you assume that there is a single 'write' instruction
as
Hi Anshuman,
Yeah I wanted to convert all these tests which are related to DSCR
into individual self tests for powerpc. All these test cases have
Anton Blanchard and IBM's copyright on it but they are licensed with
GPL V2. Not sure whether Anton needs to okay this before I can modify
them
On Wed, 2014-12-17 at 02:16 +0100, Alexander Graf wrote:
On 31.10.14 04:47, Anton Blanchard wrote:
LLVM doesn't support local named register variables and is unlikely
to. current_thread_info is using one, fix it by moving it out and
calling it __current_r1().
I gave it a bit of an
On Thu, 18 Dec 2014 16:11:54 +1100
Michael Ellerman m...@ellerman.id.au wrote:
On Wed, 2014-12-17 at 02:16 +0100, Alexander Graf wrote:
On 31.10.14 04:47, Anton Blanchard wrote:
LLVM doesn't support local named register variables and is
unlikely to. current_thread_info is using one, fix
Le 18/12/2014 03:22, Scott Wood a écrit :
On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote:
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy
Le 18/12/2014 03:14, Scott Wood a écrit :
On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote:
Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only)
bit.
This patch implements the handling of a _PAGE_RO flag to be used in place of
_PAGE_RW
Signed-off-by:
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