Dear Ajit Phadnis,
In message caknr0cilk3bfgwzuwes1khqecan6q5bpj2psn6gnmbtobcs...@mail.gmail.com
you wrote:
Would like to how to store the response command of a run command
You should ask U-Boot related questions on the U-Boot mailing list [1]
instead; chances for a helpful reply are much
Hi Folks,
Would like to how to store the response command of a run command
=setenv addr 'ping 192.172.24.24'
=setenv ping_resp 'run addr'
Would to store the outcome of run addr in into a variable and grep for
the characters or string in Uboot.
// Expecting the output as ping response
Dear Kiran,
arghhh... Please do not post the same question in several messages to
many addrresses; if you really feel you need to send it to all, then
please put all on Cc: so all can receive the replies, too.
I answered before:
In message
Hello team,
I have a problem.
In uboot, i run some IPMI commands and I have to store that value in uboot
and also extract the interim byte of the output value.
I dont see the support for the same in Uboot or I'm missing something.
eg:
uboot run IPMIcmd
The output of this has to be stored in
On (04/19/15 14:09), David Miller wrote:
On (04/18/15 21:23), Guenter Roeck wrote:
lib/built-in.o:(.discard+0x1): multiple definition of
`__pcpu_unique_iommu_pool_hash'
arch/powerpc/kernel/built-in.o:(.discard+0x18): first defined here
.. I get a similar failure in the
On Sun, 2015-04-19 at 14:36 -0400, Sowmini Varadhan wrote:
On (04/19/15 14:09), David Miller wrote:
On (04/18/15 21:23), Guenter Roeck wrote:
lib/built-in.o:(.discard+0x1): multiple definition of
`__pcpu_unique_iommu_pool_hash'
arch/powerpc/kernel/built-in.o:(.discard+0x18): first
This is a cleanup patch; doesn't change any functionality. Moves
all cpuidle related code from setup.c to a new file.
Signed-off-by: Shreyas B. Prabhu shre...@linux.vnet.ibm.com
Reviewed-by: Preeti U Murthy pre...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/Makefile | 2 +-
Currently, cpu_online_cores_map returns a mask, which for every core with
at least one online thread, has the bit for thread 0 of the core set to 1,
and the bits for all other threads of the core set to 0. But thread 0 of
the core itself may not be online always. In such cases, if the returned
Fastsleep is one of the idle state which cpuidle subsystem currently
uses on power8 machines. In this state L2 cache is brought down to a
threshold voltage. Therefore when the core is in fastsleep, the
communication between L2 and L3 needs to be fenced. But there is a bug
in the current power8
Hi Michael,
On 04/19/2015 08:01 PM, Michael Ellerman wrote:
On Sun, 2015-04-19 at 14:36 -0400, Sowmini Varadhan wrote:
On (04/19/15 14:09), David Miller wrote:
On (04/18/15 21:23), Guenter Roeck wrote:
lib/built-in.o:(.discard+0x1): multiple definition of
`__pcpu_unique_iommu_pool_hash'
Since commit 33fb845a6f01 (powerpc/8xx: Don't use MD_TWC for walk), MD_EPN and
MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 6 --
1 file changed, 6 deletions(-)
diff
L1 base address is now aligned so we can insert L1 index into r11 directly and
then preserve r10
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 34 +++---
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index aa45225..b227902e 100644
---
All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 22 ++
1 file changed, 10
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(+), 5
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index
This patchset provides a further optimisation of TLB handling in the 8xx.
Changes are:
- Not saving registers like CR when not needed
- Adding support to any TASK_SIZE
Only the last patch of the set is changed compared to v4
Resending with proper From: this time.
Christophe Leroy (5):
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
don't need to do anything at all with CR.
- We use r10, then we reload SRR0/MD_EPN into r10 when CR
Fastsleep is one of the idle state which cpuidle subsystem currently
uses on power8 machines. In this state L2 cache is brought down to a
threshold voltage. Therefore when the core is in fastsleep, the
communication between L2 and L3 needs to be fenced. But there is a bug
in the current power8
This patchset provides a further optimisation of TLB handling in the 8xx.
Main changes are based on:
- Using processor handling of PGD/PTE Validity bits instead of testing ourselves
the entries validity
- Aligning PGD address to allow direct bit manipulation
- Not saving registers like CR when not
When pages are not 4K, PGDIR table is allocated with kmalloc(). In order to
optimise TLB handlers, aligned memory is needed. kmalloc() doesn't provide
aligned memory blocks, so lets use a kmem_cache pool instead.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Kernel MMU handling code handles validity of entries via _PMD_PRESENT which
corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx
triggers TLBError exception. So we don't have to check that and branch ourself
to TLBError. We can set TLB entries with non present entries,
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
don't need to do anything at all with CR.
- If CONFIG_8xx_CPU6 is defined, we have r3 available for
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git
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