Re: [PATCH v12 01/15] PCI: Let pci_mmap_page_range() take extra resource pointer

On Fri, Jun 03, 2016 at 05:06:28PM -0700, Yinghai Lu wrote: > This one is preparing patch for next one: > PCI: Let pci_mmap_page_range() take resource addr > > We need to pass extra resource pointer to avoid searching that again > for powerpc and microblaze prot set operation. > >

[PATCH V4 2/2] cpufreq: Reuse new freq-table helpers

This patch migrates few users of cpufreq tables to the new helpers that work on sorted freq-tables. Signed-off-by: Viresh Kumar --- drivers/cpufreq/acpi-cpufreq.c | 14 -- drivers/cpufreq/amd_freq_sensitivity.c | 4 ++--

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Hi Michael, On 06 June 2016 at 02:51 AM, Michael Ellerman wrote: On Sat, 2016-06-04 at 17:07 +0200, Christian Zigotzky wrote: Aneesh, Shall I bisect the kernel from the powerpc git? No just use linus' tree. Shall I start with the following commit?

Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

On Tuesday, June 07, 2016 09:58:07 AM Viresh Kumar wrote: > On 06-06-16, 23:56, Rafael J. Wysocki wrote: > > Since you are adding new code, you can write it so it doesn't do > > unnecessary checks from the start. > > Hmm, I will do all that in this series only now. > > > While at it, the "if

Re: [PATCH] powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support call

On 31/05/16 20:32, Michael Ellerman wrote: > On Tue, 2016-05-31 at 12:19 +0200, Thomas Huth wrote: >> On 31.05.2016 12:04, Michael Ellerman wrote: >>> On Tue, 2016-05-31 at 07:51 +0200, Thomas Huth wrote: If we do not provide the PVR for POWER8NVL, a guest on this system currently ends

Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

On 08-06-16, 02:38, Rafael J. Wysocki wrote: > On Tuesday, June 07, 2016 09:58:07 AM Viresh Kumar wrote: > > On 06-06-16, 23:56, Rafael J. Wysocki wrote: > > > Since you are adding new code, you can write it so it doesn't do > > > unnecessary checks from the start. > > > > Hmm, I will do all that

[PATCH 2/5] selftests/powerpc: Add test to check TM ucontext creation

Signed-off-by: Cyril Bur --- tools/testing/selftests/powerpc/basic_asm.h| 4 + tools/testing/selftests/powerpc/fpu_asm.h | 72 tools/testing/selftests/powerpc/gpr_asm.h | 96

[PATCH 3/5] powerpc: tm: Always use fp_state and vr_state to store live registers

There is currently an inconsistency as to how the entire CPU register state is saved and restored when a thread uses transactional memory (TM). Using transactional memory results in the CPU having duplicated (almost all) of its register state. This duplication results in a set of registers which

[PATCH 1/5] selftests/powerpc: Check for VSX preservation across userspace preemption

Ensure the kernel correctly switches VSX registers correctly. VSX registers are all volatile, and despite the kernel preserving VSX across syscalls, it doesn't have to. Test that during interrupts and timeslices ending the VSX regs remain the same. Signed-off-by: Cyril Bur

[PATCH, RFC] cxl: Add support for CAPP DMA mode

From: Ian Munsie This adds support for using CAPP DMA mode, which is required for XSL based cards such as the Mellanox CX4 to function. This is currently an RFC as it depends on the corresponding support to be merged into skiboot first, which was submitted here:

Re: [PATCH 2/2] spapr: Better handling of ibm,pa-features TM bit

On Tue, Jun 07, 2016 at 10:32:10PM +1000, Anton Blanchard wrote: > From: Anton Blanchard > > There are a few issues with our handling of the ibm,pa-features > TM bit: > > - We don't support transactional memory in PR KVM, so don't tell > the OS that we do. > > - In full

Re: [PATCH 1/2] Add PowerPC AT_HWCAP2 definitions

On Tue, Jun 07, 2016 at 10:28:42PM +1000, Anton Blanchard wrote: > From: Anton Blanchard > > We need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so > add the PowerPC AT_HWCAP2 definitions. > > Signed-off-by: Anton Blanchard Applied to ppc-for-2.7.

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On Tue, 2016-06-07 at 22:17 +0200, Christian Zigotzky wrote: > > 764041e0f43cc7846f6d8eb246d65b53cc06c764 is the first bad commit > commit 764041e0f43cc7846f6d8eb246d65b53cc06c764 > Author: Aneesh Kumar K.V > Date: Fri Apr 29 23:26:09 2016 +1000 > >

Re: powerpc/mm/radix: Make the pid unsigned long

On Thu, 2016-02-06 at 09:44:48 UTC, "Aneesh Kumar K.V" wrote: > Semantic Issue: comparison of constant 18446744073709551615 with > expression of type 'unsigned int' is always false. > > Signed-off-by: Aneesh Kumar K.V > Reviewed-by: Balbir Singh

[PATCH 4/5] powerpc: tm: Rename transct_(*) to ck(\1)_state

Make the structures being used for checkpointed state named consistently with the pt_regs/ckpt_regs. Signed-off-by: Cyril Bur --- arch/powerpc/include/asm/processor.h | 20 +++- arch/powerpc/kernel/asm-offsets.c| 12 arch/powerpc/kernel/fpu.S

[PATCH 0/5] Consistent TM structures

Hi, The reason for this series is outlined in 3/5. I'll reexplain here quickly. If userspace doesn't use TM at all then pt_regs, fp_state and vr_state hold (almost) all the register state of the CPU. If userspace uses TM then pt_regs is ALWAYS the live state. This may be a transactional

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On Wed, 2016-06-08 at 00:14 +0200, Christian Zigotzky wrote: > Hi All, > > I replaced the file "slice.c" with the old one from kernel 4.6. It > compiled but unfortunately it doesn't boot. I would expect nothing else. You can't just replace whole files from different versions, the unit of work

Re: [PATCH v10 09/18] powerpc/powernv: Extend PCI bridge resources

On 20/05/16 16:41, Gavin Shan wrote: > The PCI slots are associated with root port or downstream ports > of the PCIe switch connected to root port. When adapter is hot > added to the PCI slot, it usually requests more IO or memory > resource from the directly connected parent bridge (port) and >

[PATCH 5/5] powerpc: Remove do_load_up_transact_{fpu,altivec}

Previous rework of TM code leaves these functions unused Signed-off-by: Cyril Bur --- arch/powerpc/include/asm/tm.h | 5 - arch/powerpc/kernel/fpu.S | 26 -- arch/powerpc/kernel/vector.S | 25 - 3 files changed, 56

Re: powerpc/mm/radix: Update LPCR HR bit as per ISA

On Thu, 2016-02-06 at 09:40:57 UTC, "Aneesh Kumar K.V" wrote: > We need to se HR bit LPCR for radix partitions. Please update the change log with something similar to what Ben sent. > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/reg.h | 1

[PATCH 4/8] dmaengine: s3c24xx: Simplify code in s3c24xx_dma_tx_status()

Doing so saves a few lines of code in the driver. Signed-off-by: Peter Griffin --- drivers/dma/s3c24xx-dma.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/dma/s3c24xx-dma.c b/drivers/dma/s3c24xx-dma.c index 17ccdfd..f7d2c7a 100644 ---

[PATCH 8/8] dmaengine: Remove site specific OOM error messages on kzalloc

If kzalloc() fails it will issue it's own error message including a dump_stack(). So remove the site specific error messages. Signed-off-by: Peter Griffin --- drivers/dma/amba-pl08x.c| 10 +- drivers/dma/bestcomm/bestcomm.c | 2 -- drivers/dma/edma.c

[PATCH] powerpc: Fix IBM_ARCH_VEC_NRCORES_OFFSET value

Commit 7cc851039d643a2ee7df4d18177150f2c3a484f5 "powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support call" introduced a regression by adding fields to the beginning of the ibm_architecture_vec structure without updating IBM_ARCH_VEC_NRCORES_OFFSET. This causes the kernel to

Re: [PATCH 6/6] ppc: ebpf/jit: Implement JIT compiler for extended BPF

On Tue, Jun 07, 2016 at 07:02:23PM +0530, Naveen N. Rao wrote: > PPC64 eBPF JIT compiler. > > Enable with: > echo 1 > /proc/sys/net/core/bpf_jit_enable > or > echo 2 > /proc/sys/net/core/bpf_jit_enable > > ... to see the generated JIT code. This can further be processed with >

Re: [Patch v3 4/5] fsl/qe: Add QE TDM lib

From: Zhao Qiang Date: Mon, 6 Jun 2016 14:30:01 +0800 > QE has module to support TDM, some other protocols > supported by QE are based on TDM. > add a qe-tdm lib, this lib provides functions to the protocols > using TDM to configurate QE-TDM. > > Signed-off-by: Zhao Qiang

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Hi All, I replaced the file "slice.c" with the old one from kernel 4.6. It compiled but unfortunately it doesn't boot. Cheers, Christian On 07 June 2016 at 10:17 PM, Christian Zigotzky wrote: Hi Michael, On 06 June 2016 at 02:51 AM, Michael Ellerman wrote: On Sat, 2016-06-04 at 17:07

Re: [Patch v3 5/5] drivers/net: support hdlc function for QE-UCC

From: Zhao Qiang Date: Mon, 6 Jun 2016 14:30:02 +0800 > The driver add hdlc support for Freescale QUICC Engine. > It support NMSI and TSA mode. > > Signed-off-by: Zhao Qiang Applied. ___ Linuxppc-dev mailing

[PATCH 2/8] dmaengine: fsl-edma: print error code in error messages.

It is useful to print the error code as part of the error message. Signed-off-by: Peter Griffin --- drivers/dma/fsl-edma.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c index 7208fc9..cc06eea

[PATCH 6/8] dmaengine: sun6i-dma: Only calculate residue if state exists.

There is no point in calculating the residue if state does not exist to store the value. Signed-off-by: Peter Griffin --- drivers/dma/sun6i-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index

Re: [Patch v3 2/5] fsl/qe: setup clock source for TDM mode

From: Zhao Qiang Date: Mon, 6 Jun 2016 14:29:59 +0800 > Add tdm clock configuration in both qe clock system and ucc > fast controller. > > Signed-off-by: Zhao Qiang Applied. ___ Linuxppc-dev mailing list

[PATCH 1/8] dmaengine: fsl-edma: Fix clock handling error paths

Currently fsl-edma doesn't clk_disable_unprepare() its clocks on error conditions. This patch adds a fsl_disable_clocks helper for this, and also only disables clocks which were enabled if encountering an error whilst enabling clocks. Signed-off-by: Peter Griffin ---

[PATCH 5/8] dmaengine: ste_dma40: Only calculate residue if txstate exists.

There is no point calculating the residue if there is no txstate to store the value. Signed-off-by: Peter Griffin --- drivers/dma/ste_dma40.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index

[PATCH 7/8] dmaengine: tegra20-apb-dma: Only calculate residue if txstate exists.

There is no point calculating the residue if there is no txstate to store the value. Signed-off-by: Peter Griffin --- drivers/dma/tegra20-apb-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/tegra20-apb-dma.c

[PATCH 0/8] Various dmaengine cleanups

Hi Vinod, This series is a bunch of cleanup updates to various dmaengine drivers, based on some of the review feeback to my fdma series. regards, Peter. Peter Griffin (8): dmaengine: fsl-edma: Fix clock handling error paths dmaengine: fsl-edma: print error code in error messages.

[PATCH 3/8] dmaengine: coh901318: Only calculate residue if txstate exists.

There is no point in calculating the residue if there is no txstate to store the value. Signed-off-by: Peter Griffin --- drivers/dma/coh901318.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c index

Re: [Patch v3 3/5] fsl/qe: Make regs resouce_size_t

From: Zhao Qiang Date: Mon, 6 Jun 2016 14:30:00 +0800 > Signed-off-by: Zhao Qiang Applied. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [Patch v3 1/5] fsl/qe: add rx_sync and tx_sync for TDM mode

From: Zhao Qiang Date: Mon, 6 Jun 2016 14:29:58 +0800 > Rx_sync and tx_sync are used by QE-TDM mode, > add them to struct ucc_fast_info. > > Signed-off-by: Zhao Qiang Applied. ___ Linuxppc-dev mailing list

Re: [PATCH] powerpc/mm/hash: Fix the reference bit update when handling hash fault

On Thu, 2016-06-02 at 08:12 -0700, Hugh Dickins wrote: > On Tue, 31 May 2016, Hugh Dickins wrote: > > > > But all my evidence so far is that it is now right: I'll continue > > testing v4.6+fix on a couple of loads until this evening: all is > > well so far. And then switch to testing v4.5+fix on

[PATCH 4/6] ppc: bpf/jit: A few cleanups

1. Per the ISA, ADDIS actually uses RT, rather than RS. Though the result is the same, make the usage clear. 2. The multiply instruction used is a 32-bit multiply. Rename PPC_MUL() to PPC_MULW() to make the same clear. 3. PPC_STW[U] take the entire 16-bit immediate value and do not require

[PATCH 5/6] ppc: bpf/jit: Isolate classic BPF JIT specifics into a separate header

Break out classic BPF JIT specifics into a separate header in preparation for eBPF JIT implementation. Note that ppc32 will still need the classic BPF JIT. Cc: Matt Evans Cc: Denis Kirjanov Cc: Michael Ellerman Cc: Paul Mackerras

[PATCH 1/2] Add PowerPC AT_HWCAP2 definitions

From: Anton Blanchard We need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so add the PowerPC AT_HWCAP2 definitions. Signed-off-by: Anton Blanchard --- diff --git a/include/elf.h b/include/elf.h index 28d448b..8533b2a 100644 --- a/include/elf.h +++

[PATCH 0/6] eBPF JIT for PPC64

Implement extended BPF JIT for ppc64. We retain the classic BPF JIT for ppc32 and move ppc64 BE/LE to use the new JIT. Classic BPF filters will be converted to extended BPF (see convert_filter()) and JIT'ed with the new compiler. Most of the existing macros are retained and fixed/enhanced where

Re: [RFC v3 20/45] xen: dma-mapping: Use unsigned long for dma_attrs

On 02/06/16 16:39, Krzysztof Kozlowski wrote: > Split out subsystem specific changes for easier reviews. This will be > squashed with main commit. Acked-by: David Vrabel David ___ Linuxppc-dev mailing list

[PATCH 2/2] spapr: Better handling of ibm,pa-features TM bit

From: Anton Blanchard There are a few issues with our handling of the ibm,pa-features TM bit: - We don't support transactional memory in PR KVM, so don't tell the OS that we do. - In full emulation we have a minimal implementation of TM that always fails, so for

Re: [PATCH 2/2] KVM: PPC: hypervisor large decrementer support

On Fri, 2016-06-03 at 07:46 +1000, Benjamin Herrenschmidt wrote: > On Wed, 2016-06-01 at 16:23 +1000, Michael Neuling wrote: > > FWIW you can use: > > andis. reg,reg,(LPCR_LD)@ha > > @h in that case. Probably the same result but technically @ha is for > arithmetic operations. In this

[PATCH 2/6] ppc: bpf/jit: Optimize 64-bit Immediate loads

Similar to the LI32() optimization, if the value can be represented in 32-bits, use LI32(). Also handle loading a few specific forms of immediate values in an optimum manner. Cc: Matt Evans Cc: Denis Kirjanov Cc: Michael Ellerman

[PATCH 6/6] ppc: ebpf/jit: Implement JIT compiler for extended BPF

PPC64 eBPF JIT compiler. Enable with: echo 1 > /proc/sys/net/core/bpf_jit_enable or echo 2 > /proc/sys/net/core/bpf_jit_enable ... to see the generated JIT code. This can further be processed with tools/net/bpf_jit_disasm. With CONFIG_TEST_BPF=m and 'modprobe test_bpf': test_bpf: Summary: 305

Re: powerpc/nvram: Fix an incorrect partition merge

On Mon, 2016-06-06 at 13:31 +0800, xinhui wrote: > On 2016年06月03日 19:47, Michael Ellerman wrote: > > On Thu, 2015-10-12 at 07:30:02 UTC, xinhui wrote: > > > From: Pan Xinhui > > > > > > When we merge two contiguous partitions whose signatures are marked > > >

[PATCH 1/6] ppc: bpf/jit: Fix/enhance 32-bit Load Immediate implementation

The existing LI32() macro can sometimes result in a sign-extended 32-bit load that does not clear the top 32-bits properly. As an example, loading 0x7fff results in the register containing 0x7fff. While this does not impact classic BPF JIT implementation (since that only uses the

[PATCH 3/6] ppc: bpf/jit: Introduce rotate immediate instructions

Since we will be using the rotate immediate instructions for extended BPF JIT, let's introduce macros for the same. And since the shift immediate operations use the rotate immediate instructions, let's redo those macros to use the newly introduced instructions. Cc: Matt Evans

[PATCH 2/2] workqueue:Fix affinity of an unbound worker of a node with 1 online CPU

With commit e9d867a67fd03ccc ("sched: Allow per-cpu kernel threads to run on online && !active"), __set_cpus_allowed_ptr() expects that only strict per-cpu kernel threads can have affinity to an online CPU which is not yet active. This assumption is currently broken in the CPU_ONLINE notification

[PATCH 1/2] workqueue: Move wq_update_unbound_numa() to the beginning of CPU_ONLINE

Currently in the CPU_ONLINE workqueue handler, the restore_unbound_workers_cpumask() will never call set_cpus_allowed_ptr() for a newly created unbound worker thread. This is because the function which creates a new unbound worker thread when the first CPU in the node comes online

[PATCH 0/2] Fix CPU Online handling for unbounded worker threads

Hi, This patchset fixes a couple of issues in the CPU_ONLINE notification handling for the workqueues with respect to unbounded worker threads. Patch 1 ensures that the affinity of a unbound worker thread associated with a node whose very first CPU has come online is set correctly. In the

[PATCH v12.update 02/15] PCI: Let pci_mmap_page_range() take resource address

In 8c05cd08a7 ("PCI: fix offset check for sysfs mmapped files"), try to check exposed value with resource start/end in proc mmap path. |start = vma->vm_pgoff; |size = ((pci_resource_len(pdev, resno) - 1) >> PAGE_SHIFT) + 1; |pci_start = (mmap_api == PCI_MMAP_PROCFS) ? |

[PATCH v12.update 01/15] PCI: Let pci_mmap_page_range() take extra resource pointer

This one is preparing patch for next one: PCI: Let pci_mmap_page_range() take resource addr We need to pass extra resource pointer to avoid searching that again for powerpc and microblaze prot set operation. update for fixing bisectibility problem found by build test robot. Signed-off-by: