[PATCH 2/3] hwmon: ibmpowernv: Add attributes to enable/disable sensor groups

On-Chip-Controller(OCC) is an embedded micro-processor in POWER9 chip which measures various system and chip level sensors. These sensors comprises of environmental sensors (like power, temperature, current and voltage) and performance sensors (like utilization, frequency). All these sensors are

[PATCH v3 5/6] powerpc64/ftrace: Use the generic version of ftrace_replace_code()

Our implementation matches that of the generic version, which also handles FTRACE_UPDATE_MODIFY_CALL. So, remove our implementation in favor of the generic version. Signed-off-by: Naveen N. Rao --- arch/powerpc/kernel/trace/ftrace.c | 36

[PATCH v3 0/6] powerpc64/ftrace: Add support for ftrace_modify_call() and a few other fixes

This is v3 of the patches posted at: https://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg130652.html This series has been tested using mambo for p8 (hash) and p9 (radix). The first two patches fix a kernel oops when function tracing is enabled while using KVM. Patch 3 is new and

[PATCH v3 3/6] powerpc/kexec: Disable ftrace before switching to the new kernel

If function_graph tracer is enabled during kexec, we see the below exception in the simulator: root@(none):/# kexec -e kvm: exiting hardware virtualization kexec_core: Starting new kernel [ 19.262020070,5] OPAL: Switch to big-endian OS kexec: Starting

RE: RFC on writel and writel_relaxed

From: Oliver > Sent: 22 March 2018 05:24 ... > > No less painful was doing a byteswapping write to normal memory. > > What was the problem? The reverse indexed load/store instructions are > a little awkward to use, but they work... Finding something that would generate the right instruction

Re: [PATCH V5 3/4] powerpc/mm/hash64: Increase the VA range

"Aneesh Kumar K.V" writes: > diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c > index fdb424a29f03..63470b06c502 100644 > --- a/arch/powerpc/mm/init_64.c > +++ b/arch/powerpc/mm/init_64.c > @@ -68,12 +68,6 @@ > > #include "mmu_decl.h" > >

[PATCH 3/3] powernv: opal-sensor-groups: Add attributes to disable/enable sensors

This patch provides support to disable and enable plaform specific sensor groups like performance, utilization and frequency. Signed-off-by: Shilpasri G Bhat --- .../ABI/testing/sysfs-firmware-opal-sensor-groups | 34 +

[PATCH v3 6/6] powerpc64/ftrace: Implement support for ftrace_regs_caller()

With -mprofile-kernel, we always save the full register state in ftrace_caller(). While this works, this is inefficient if we're not interested in the register state, such as when we're using the function tracer. Rename the existing ftrace_caller() as ftrace_regs_caller() and provide a simpler

[PATCH 1/3] powernv:opal-sensor-groups: Add support to enable sensor groups

Adds support to enable/disable a sensor group at runtime. This can be used to select the sensor groups that needs to be copied to main memory by OCC. Sensor groups like power, temperature, current, voltage, frequency, utilization can be enabled/disabled at runtime. Signed-off-by: Shilpasri G Bhat

Re: RFC on writel and writel_relaxed

On Thu, Mar 22, 2018 at 3:24 PM, Benjamin Herrenschmidt wrote: > On Wed, 2018-03-21 at 08:53 -0500, Sinan Kaya wrote: >> writel_relaxed() needs to have ordering guarantees with respect to the order >> device observes writes. > > Correct. > >> x86 has compiler barrier

[PATCH v3 1/6] powerpc64/ftrace: Add a field in paca to disable ftrace in unsafe code paths

We have some C code that we call into from real mode where we cannot take any exceptions. Though the C functions themselves are mostly safe, if these functions are traced, there is a possibility that we may take an exception. For instance, in certain conditions, the ftrace code uses WARN(), which

Re: RFC on writel and writel_relaxed

On Thu, Mar 22, 2018 at 08:25:43PM +1100, Oliver wrote: > On Thu, Mar 22, 2018 at 7:20 PM, Gabriel Paubert wrote: > > On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote: > >> On Thu, Mar 22, 2018 at 1:35 AM, David Laight > >> wrote: > >> >> x86 has

Re: [PATCH V5 4/4] powerpc/mm/hash: Don't memset pgd table if not needed

"Aneesh Kumar K.V" writes: > We need to zero-out pgd table only if we share the slab cache with pud/pmd > level caches. With the support of 4PB, we don't share the slab cache anymore. > Instead of removing the code completely hide it within an #ifdef. We don't >

[PATCH 0/3] Add support to disable sensor groups in P9

This patch series adds support to enable/disable OCC based inband-sensor groups at runtime. The environmental sensor groups are managed in HWMON and the remaining platform specific sensor groups are managed in /sys/firmware/opal. The firmware changes required for this patch is posted below:

Re: RFC on writel and writel_relaxed

On Thu, Mar 22, 2018 at 7:20 PM, Gabriel Paubert wrote: > On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote: >> On Thu, Mar 22, 2018 at 1:35 AM, David Laight >> wrote: >> >> x86 has compiler barrier inside the relaxed() API so that code does not >>

[PATCH v2] crypto: talitos - fix IPsec cipher in length

For SEC 2.x+, cipher in length must contain only the ciphertext length. In case of using hardware ICV checking, the ICV length is provided via the "extent" field of the descriptor pointer. Cc: # 4.8+ Fixes: 549bd8bc5987 ("crypto: talitos - Implement AEAD for SEC1 using

[PATCH] powerpc: Fix smp_wmb barrier definition use use lwsync consistently

asm/barrier.h is not always included after asm/synch.h, which meant it was missing __SUBARCH_HAS_LWSYNC, so in some files smp_wmb() would be eieio when it should be lwsync. kernel/time/hrtimer.c is one case. __SUBARCH_HAS_LWSYNC is only used in one place, so just fold it in to where it's used.

Re: RFC on writel and writel_relaxed

On Thu, 2018-03-22 at 21:15 +1100, Oliver wrote: > On Thu, Mar 22, 2018 at 3:24 PM, Benjamin Herrenschmidt > wrote: > > On Wed, 2018-03-21 at 08:53 -0500, Sinan Kaya wrote: > > > writel_relaxed() needs to have ordering guarantees with respect to the > > > order > > >

Re: DMA Mapping Error in ppc64

Thank you for the response but unfortunately, it looks like I already have that and it is being used. To verify, I commented that out and got the failure "dma_direct_alloc_coherent: No suitable zone for pfn 0xe". Below is the code flow for function ath10k_pci_hif_exchange_bmi_msg which is

[PATCH v3 2/6] powerpc64/ftrace: Disable ftrace during kvm guest entry/exit

During guest entry/exit, we switch over to/from the guest MMU context. While doing so, we set our state to KVM_GUEST_MODE_HOST_HV to note down the fact that we cannot take any exceptions in the hypervisor code. Since ftrace may be enabled and since it can result in us taking a trap, disable

[PATCH v3 4/6] powerpc64/module: Tighten detection of mcount call sites with -mprofile-kernel

For R_PPC64_REL24 relocations, we suppress emitting instructions for TOC load/restore in the relocation stub if the relocation is for _mcount() call when using -mprofile-kernel ABI. To detect this, we check if the preceding instructions are per the standard set of instructions emitted by gcc:

[RFC][PATCH] powerpc/64s: rewriting interrupt entry code

Long long post ahead... I've been playing with rewriting interrupt entry code, this is really rough patch so far, but it boots mambo. I'll just post it now to get opinions on the approach. This implements a new set of exception macros, converts the decrementer to use them (it's maskable so it

Re: [PATCH v2 09/38] cxlflash: Setup AFU acTag range

Le 26/02/2018 à 23:21, Uma Krishnan a écrit : The OCXL specification supports distributing acTags amongst different AFUs and functions on the link. As cxlflash devices are expected to only support a single AFU and function, the entire range that was assigned to the function is also assigned to

Re: [PATCH v2 11/38] cxlflash: Adapter context support for OCXL

Le 26/02/2018 à 23:21, Uma Krishnan a écrit : Add support to create and release the adapter contexts for OCXL and provide means to specify certain contexts as a master. The existing cxlflash core has a design requirement that each host will have a single host context available by default. To

[PATCH] cxl: disable the lazy approach for irqs in POWERVM environment.

The cxl driver cannot disable the interrupt at the device level and has to use disable_irq[_nosync] instead. To avoid the implementation of the lazy optimisation (the interrupt is marked disabled, but the hardware is left unmasked), we can disable it, for a particular irq line, by calling

Re: [PATCH v2 19/38] cxlflash: Support AFU state toggling

Le 26/02/2018 à 23:22, Uma Krishnan a écrit : The AFU should be enabled following a successful configuration and disabled near the end of the cleanup path. Signed-off-by: Uma Krishnan Acked-by: Matthew R. Ochs --- Reviewed-by:

Re: [PATCH v2 07/38] cxlflash: Setup function acTag range

Le 26/02/2018 à 23:20, Uma Krishnan a écrit : The OCXL specification supports distributing acTags amongst different AFUs and functions on the link. The platform-specific acTag range for the link is obtained using the OCXL provider services and then assigned to the host function based on

Re: [PATCH v2 08/38] cxlflash: Read host AFU configuration

Le 26/02/2018 à 23:21, Uma Krishnan a écrit : The host AFU configuration is read on the initialization path to identify the features and configuration of the AFU. This data is cached for use in later configuration steps. Signed-off-by: Uma Krishnan Acked-by:

Re: [PATCH v2 06/38] cxlflash: Read host function configuration

Le 26/02/2018 à 23:20, Uma Krishnan a écrit : Per the OCXL specification, the underlying host can have multiple AFUs per function with each function supporting its own configuration. The host function configuration is read on the initialization path to evaluate the number of functions present

Re: [PATCH v2 08/38] cxlflash: Read host AFU configuration

Le 26/02/2018 à 23:21, Uma Krishnan a écrit : The host AFU configuration is read on the initialization path to identify the features and configuration of the AFU. This data is cached for use in later configuration steps. Signed-off-by: Uma Krishnan Acked-by:

Re: [PATCH v2 13/38] cxlflash: Support adapter file descriptors for OCXL

Le 26/02/2018 à 23:21, Uma Krishnan a écrit : Allocate a file descriptor for an adapter context when requested. In order to allocate inodes for the file descriptors, a pseudo filesystem is created and used. Signed-off-by: Uma Krishnan Acked-by: Matthew R. Ochs

Re: [PATCH v2 16/38] cxlflash: MMIO map the AFU

Le 26/02/2018 à 23:22, Uma Krishnan a écrit : When the AFU is configured, the global and per process MMIO regions are presented by the configuration space. Save these regions and map the global MMIO region that is used to access all of the control and provisioning data in the AFU.

Re: [PATCH v2 10/38] cxlflash: Setup AFU PASID

Le 26/02/2018 à 23:21, Uma Krishnan a écrit : Per the OCXL specification, the maximum PASID supported by the AFU is indicated by a field within the configuration space. Similar to acTags, implementations can choose to use any sub-range of PASID within their assigned range. For cxlflash, the

[RFC PATCH v2 0/2] Randomization of address chosen by mmap.

Current implementation doesn't randomize address returned by mmap. All the entropy ends with choosing mmap_base_addr at the process creation. After that mmap build very predictable layout of address space. It allows to bypass ASLR in many cases. This patch make randomization of address on any mmap

[RFC PATCH v2 1/2] Randomization of address chosen by mmap.

Signed-off-by: Ilya Smith --- include/linux/mm.h | 16 -- mm/mmap.c | 164 + 2 files changed, 175 insertions(+), 5 deletions(-) diff --git a/include/linux/mm.h b/include/linux/mm.h index ad06d42..c716257

Re: [trivial PATCH V2] treewide: Align function definition open/close braces

On Wed, 21 Mar 2018 15:09:32 -0700 Joe Perches wrote: > diff --git a/kernel/trace/trace_printk.c b/kernel/trace/trace_printk.c > index ad1d6164e946..50f44b7b2b32 100644 > --- a/kernel/trace/trace_printk.c > +++ b/kernel/trace/trace_printk.c > @@ -196,7 +196,7 @@ struct

Re: [PATCH v2 21/38] cxlflash: Setup function OCXL link

Le 26/02/2018 à 23:22, Uma Krishnan a écrit : After reading and modifying the function configuration, setup the OCXL link using the OCXL provider services. The link is released when the adapter is unconfigured. Signed-off-by: Uma Krishnan Acked-by: Matthew R. Ochs

Re: RFC on writel and writel_relaxed

On 3/22/2018 8:52 AM, Benjamin Herrenschmidt wrote: >>> No, it's not sufficient. > Just to clarify ... barrier() is just a compiler barrier, it means the > compiler will generate things in the order they are written. This isn't > sufficient on archs with an OO memory model, where an actual memory

[RFC PATCH v2 2/2] Architecture defined limit on memory region random shift.

Signed-off-by: Ilya Smith --- arch/alpha/kernel/osf_sys.c | 1 + arch/arc/mm/mmap.c | 1 + arch/arm/mm/mmap.c | 2 ++ arch/frv/mm/elf-fdpic.c | 1 + arch/ia64/kernel/sys_ia64.c | 1 + arch/ia64/mm/hugetlbpage.c

[PATCH 00/19] powerpc/ppc32: make W=1 compilation errors free

Here is another batch for warnings treated as error on ppc32. Tested with: $ make ARCH=powerpc ppc32_defconfig $ make -j8 ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- W=1 Using: $ powerpc-linux-gnu-gcc --version powerpc-linux-gnu-gcc (Debian 6.3.0-18) 6.3.0 20170516 Mathieu Malaterre (19):

[PATCH 01/19] powerpc/powermac: Mark variable x as unused

Since the value of x is never intended to be read, declare it with gcc attribute as unused. Fix warning treated as error with W=1: arch/powerpc/platforms/powermac/bootx_init.c:471:21: error: variable ‘x’ set but not used [-Werror=unused-but-set-variable] Signed-off-by: Mathieu Malaterre

[PATCH 08/19] powerpc/tau: Make some function static

These functions can all be static, make it so. Fix warnings treated as errors with W=1: arch/powerpc/kernel/tau_6xx.c:53:6: error: no previous prototype for ‘set_thresholds’ [-Werror=missing-prototypes] arch/powerpc/kernel/tau_6xx.c:73:6: error: no previous prototype for ‘TAUupdate’

Re: [PATCH v2 12/38] cxlflash: Use IDR to manage adapter contexts

Le 26/02/2018 à 23:21, Uma Krishnan a écrit : A range of PASIDs are used as identifiers for the adapter contexts. These contexts may be destroyed and created randomly. Use an IDR to keep track of contexts that are in use and assign a unique identifier to new ones. Signed-off-by: Uma Krishnan

[PATCH 03/19] powerpc: Mark variables as unused

Add gcc attribute unused for two variables. Fix warnings treated as errors with W=1: arch/powerpc/kernel/prom_init.c:1388:8: error: variable ‘path’ set but not used [-Werror=unused-but-set-variable] Signed-off-by: Mathieu Malaterre --- arch/powerpc/kernel/prom_init.c | 4

[PATCH 04/19] powerpc/kvm: Mark variable tmp unused

Add gcc attribute unused to variable tmp. Fix warning treated as error with W=1: arch/powerpc/kernel/kvm.c:675:6: error: variable ‘tmp’ set but not used [-Werror=unused-but-set-variable] Signed-off-by: Mathieu Malaterre --- arch/powerpc/kernel/kvm.c | 2 +- 1 file changed,

[PATCH 05/19] powerpc/chrp/setup: Add attribute unused and make some functions static

Add gcc attribute unused to silence a warning. These functions can all be static, make it so. Fix warnings treated as errors with W=1: arch/powerpc/platforms/chrp/setup.c:97:6: error: no previous prototype for ‘chrp_show_cpuinfo’ [-Werror=missing-prototypes]

[PATCH 06/19] powerpc: Make function btext_initialize static

This function can be static, make it so, this fix a warning treated as error with W=1: arch/powerpc/kernel/btext.c:173:5: error: no previous prototype for ‘btext_initialize’ [-Werror=missing-prototypes] Signed-off-by: Mathieu Malaterre --- arch/powerpc/kernel/btext.c | 2

[PATCH 11/19] powerpc/powermac: Move pmac_pfunc_base_install prototype to header file

The pmac_pfunc_base_install prototype was declared in powermac/smp.c since function was used there, move it to pmac_pfunc.h header to be visible in pfunc_base.c. Fix a warning treated as error with W=1: arch/powerpc/platforms/powermac/pfunc_base.c:330:12: error: no previous prototype for

[PATCH 12/19] powerpc/powermac: Add missing prototype for note_bootable_part()

Add a missing prototype for function `note_bootable_part` to silence a warning treated as error with W=1: arch/powerpc/platforms/powermac/setup.c:361:12: error: no previous prototype for ‘note_bootable_part’ [-Werror=missing-prototypes] Signed-off-by: Mathieu Malaterre ---

[PATCH 15/19] powerpc: Add missing prototype

Add one missing prototype for function rh_dump_blk. Fix warning treated as error in W=1: arch/powerpc/lib/rheap.c:740:6: error: no previous prototype for ‘rh_dump_blk’ [-Werror=missing-prototypes] Signed-off-by: Mathieu Malaterre --- arch/powerpc/include/asm/rheap.h | 3

[PATCH 17/19] powerpc/32: Add a missing include header

The header file was missing from the includes. Fix the following warning, treated as error with W=1: arch/powerpc/kernel/pci_32.c:286:6: error: no previous prototype for ‘sys_pciconfig_iobase’ [-Werror=missing-prototypes] Signed-off-by: Mathieu Malaterre ---

[PATCH 18/19] powerpc: Add a missing include header

The header file was missing from the includes. Fix the following warning, treated as error with W=1: arch/powerpc/kernel/vecemu.c:260:5: error: no previous prototype for ‘emulate_altivec’ [-Werror=missing-prototypes] Signed-off-by: Mathieu Malaterre ---

[PATCH] PCI/IOV: Add missing prototype for powerpc specific

Some prototypes for weak functions were missing for powerpc specific functions. Add the missing prototypes to the CONFIG_PCI_IOV block. This fixes the following three warnings treated as error when using W=1: arch/powerpc/kernel/pci-common.c:236:17: error: no previous prototype for

[PATCH] powerpc/mm/radix: Fix always false comparison against MMU_NO_CONTEXT

In commit 9690c1574268 ("powerpc/mm/radix: Fix always false comparison against MMU_NO_CONTEXT") an issue was discovered where `mm->context.id` was being truncated to an `unsigned int`, while the PID is actually an `unsigned long`. Update the earlier patch by fixing one remaining occurrence.

[PATCH 09/19] powerpc/chrp/pci: Make some functions static

These functions can all be static, make it so. Fix warnings treated as errors with W=1: arch/powerpc/platforms/chrp/pci.c:34:5: error: no previous prototype for ‘gg2_read_config’ [-Werror=missing-prototypes] arch/powerpc/platforms/chrp/pci.c:61:5: error: no previous prototype for

[PATCH 10/19] powerpc/chrp/time: Make some functions static, add missing header include

Add a missing include . These functions can all be static, make it so. Fix warnings treated as errors with W=1: arch/powerpc/platforms/chrp/time.c:41:13: error: no previous prototype for ‘chrp_time_init’ [-Werror=missing-prototypes] arch/powerpc/platforms/chrp/time.c:66:5: error: no

[PATCH 13/19] powerpc/52xx: Add missing functions prototypes

The function prototypes were declared within a `#ifdef CONFIG_PPC_LITE5200` block which would prevent them from being visible when compiling `mpc52xx_pm.c`. Move the prototypes outside of the `#ifdef` block to fix the following warnings treated as errors with W=1:

[PATCH 14/19] powerpc/altivec: Add missing prototypes for altivec

Some functions prototypes were missing for the non-altivec code. Add the missing prototypes directly in xor_vmx, fix warnings treated as errors with W=1: arch/powerpc/lib/xor_vmx_glue.c:18:6: error: no previous prototype for ‘xor_altivec_2’ [-Werror=missing-prototypes]

[PATCH 16/19] powerpc/powermac: Add missing include of header pmac.h

The header `pmac.h` was not included, leading to the following warnings, treated as error with W=1: arch/powerpc/platforms/powermac/time.c:69:13: error: no previous prototype for ‘pmac_time_init’ [-Werror=missing-prototypes] arch/powerpc/platforms/powermac/time.c:207:15: error: no previous

[PATCH 19/19] powerpc/tau: Synchronize function prototypes and body

Some function prototypes and body for Thermal Assist Units were not in sync. Update the function definition to match the existing function declaration found in `setup-common.c`, changing an `int` return type to a `u32` return type. Move the prototypes to a header file. Fix the following warnings,

Re: [RFC PATCH v2 1/2] Randomization of address chosen by mmap.

On Thu, 22 Mar 2018 19:36:37 +0300 Ilya Smith wrote: > include/linux/mm.h | 16 -- > mm/mmap.c | 164 > + You'll be wanting to update the documentation. Documentation/sysctl/kernel.txt and

Re: [RFC PATCH v2 2/2] Architecture defined limit on memory region random shift.

Please add changelogs. An explanation of what a "limit on memory region random shift" is would be nice ;) Why does it exist, why are we doing this, etc. Surely there's something to be said - at present this is just a lump of random code?

Re: [RFC PATCH v2 0/2] Randomization of address chosen by mmap.

On Thu, 22 Mar 2018 19:36:36 +0300 Ilya Smith wrote: > Current implementation doesn't randomize address returned by mmap. > All the entropy ends with choosing mmap_base_addr at the process > creation. After that mmap build very predictable layout of address > space. It

Re: [PATCH v6 02/12] PKCS#7: Introduce pkcs7_get_message_sig() and verify_pkcs7_message_sig()

Hi Thiago, On Fri, 2018-03-16 at 17:38 -0300, Thiago Jung Bauermann wrote: > IMA will need to know the key that signed a given PKCS#7 message, so add > pkcs7_get_message_sig(). > > It will also need to verify an already parsed PKCS#7 message. For this > purpose, add verify_pkcs7_message_sig()

[PATCH] cxl: remove a dead branch

In commit 14baf4d9c739 ("cxl: Add guest-specific code") the following code was added: if (afu->crs_len < 0) { dev_err(>dev, "Unexpected configuration record size value\n"); return -EINVAL; } However the variable `crs_len` is of type u64 and cannot

Re: [PATCH v2 1/5] powerpc64/ftrace: Add a field in paca to disable ftrace in unsafe code paths

Naveen N. Rao wrote: We have some C code that we call into from real mode where we cannot take any exceptions. Though the C functions themselves are mostly safe, if these functions are traced, there is a possibility that we may take an exception. For instance, in certain conditions, the ftrace

Re: RFC on writel and writel_relaxed

On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote: > On Thu, Mar 22, 2018 at 1:35 AM, David Laight wrote: > >> x86 has compiler barrier inside the relaxed() API so that code does not > >> get reordered. ARM64 architecturally guarantees device writes to be > >>

[PATCH V2] powerpc/mm/radix: Update pte fragment count from 16 to 256 on radix

Right now we use only 4K out of the 64k page allocated for the level 4 page table. W.r.t the performance impact due to lock contention, with ebizzy 256 threads: without patch (10 runs of ./ebizzy -m -n 1000 -s 131072 -S 100) median = 15678.5 stdev = 42.1209 with patch: median = 15354 stdev =

Re: DMA Mapping Error in ppc64

On Fri, Mar 23, 2018 at 1:37 AM, Jared Bents wrote: > Thank you for the response but unfortunately, it looks like I already > have that and it is being used. To verify, I commented that out and > got the failure "dma_direct_alloc_coherent: No suitable zone for

[PATCH] powerpc/eeh: Avoid misleading message "EEH: no capable adapters found"

Due to recent refactoring in EEH in: commit b9fde58db7e5 ("powerpc/powernv: Rework EEH initialization on powernv") a misleading message was seen in the kernel message buffer: [0.108431] EEH: PowerNV platform initialized [0.589979] EEH: No capable adapters found This happened due to the

Re: RFC on writel and writel_relaxed

On Thu, 2018-03-22 at 12:51 -0500, Sinan Kaya wrote: > On 3/22/2018 8:52 AM, Benjamin Herrenschmidt wrote: > > > > No, it's not sufficient. > > > > Just to clarify ... barrier() is just a compiler barrier, it means the > > compiler will generate things in the order they are written. This isn't >

Re: [PATCH] cxl: disable the lazy approach for irqs in POWERVM environment.

On Thu, 2018-03-22 at 17:37 +0100, Christophe Lombard wrote: > The cxl driver cannot disable the interrupt at the device level and has > to use disable_irq[_nosync] instead. > To avoid the implementation of the lazy optimisation (the interrupt is > marked disabled, but the hardware is left

Re: [PATCH v2 12/38] cxlflash: Use IDR to manage adapter contexts

> On Mar 22, 2018, at 11:40 AM, Frederic Barrat > wrote: > > > > Le 26/02/2018 à 23:21, Uma Krishnan a écrit : >> A range of PASIDs are used as identifiers for the adapter contexts. These >> contexts may be destroyed and created randomly. Use an IDR to keep track

Re: [PATCH v6 03/12] PKCS#7: Introduce pkcs7_get_digest()

On Fri, 2018-03-16 at 17:38 -0300, Thiago Jung Bauermann wrote: > IMA will need to access the digest of the PKCS7 message (as calculated by > the kernel) before the signature is verified, so introduce > pkcs7_get_digest() for that purpose. > > Also, modify pkcs7_digest() to detect when the digest

[PATCH] powerpc/eeh: Fix race with driver un/bind

The current EEH callbacks can race with a driver unbind. This can result in a backtraces like this: [7.573055] EEH: Frozen PHB#0-PE#1fc detected [7.573063] EEH: PE location: S09, PHB location: N/A [7.573069] CPU: 2 PID: 2312 Comm: kworker/u258:3 Not tainted 4.15.6-openpower1 #2 [

[PATCH 1/3] powerpc/mm/radix: Remove unused code

These function are not used in the code. Remove them. Signed-off-by: Aneesh Kumar K.V --- .../powerpc/include/asm/book3s/64/tlbflush-radix.h | 3 -- arch/powerpc/mm/tlb-radix.c| 40 -- 2 files changed, 43 deletions(-)

Re: [PATCH 3/3] powerpc/mm: Fixup tlbie vs store ordering issue on POWER9

"Aneesh Kumar K.V" writes: > diff --git a/arch/powerpc/include/asm/cputable.h > b/arch/powerpc/include/asm/cputable.h > index a2c5c95882cf..6c151d2e9bd9 100644 > --- a/arch/powerpc/include/asm/cputable.h > +++ b/arch/powerpc/include/asm/cputable.h > @@ -465,7

[PATCH] powerpc/64s: Fix i-side SLB miss bad address handler saving nonvolatile GPRs

The SLB bad address handler's trap number fixup does not preserve the low bit that indicates nonvolatile GPRs have not been saved. This leads save_nvgprs to skip saving them, and subsequent functions and return from interrupt will think they are saved. This causes kernel branch-to-garbage

[PATCH 3/3] powerpc/mm: Fixup tlbie vs store ordering issue on POWER9

On POWER9, under some circumstances, a broadcast TLB invalidation might complete before all previous stores have drained, potentially allowing stale stores from becoming visible after the invalidation. This works around it by doubling up those TLB invalidations which was verified by HW to be

Re: [PATCHv5 0/3] enable nr_cpus for powerpc

Maintainers, ping? Any comment? Thanks On Thu, Mar 15, 2018 at 12:41 PM, Pingfan Liu wrote: > This topic has a very long history. It comes from Mahesh Salgaonkar > > For v3: https://patchwork.ozlabs.org/patch/834860/ > I hope we can acquire it

[PATCH 2/3] powerpc/mm/radix: Move the functions that does the actual tlbie closer

No functionality change. Just code movement to ease code changes later Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/tlb-radix.c | 64 ++--- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git

Re: [PATCH 2/2] powerpc/time: Only set ARCH_HAS_SCALED_CPUTIME on PPC64

Hi Christophe, Thank you for the patch! Yet something to improve: [auto build test ERROR on powerpc/next] [also build test ERROR on v4.16-rc6 next-20180322] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci

[PATCH 1/2] powerpc/mm: Add tracking of the number of coprocessors using a context

From: Benjamin Herrenschmidt Currently, when using coprocessors (which use the Nest MMU), we simply increment the active_cpu count to force all TLB invalidations to be come broadcast. Unfortunately, due to an errata in POWER9, we will need to know more specifically

[PATCH 2/2] powerpc/mm: Workaround Nest MMU bug with TLB invalidations

From: Benjamin Herrenschmidt On POWER9 the Nest MMU may fail to invalidate some translations when doing a tlbie "by PID" or "by LPID" that is targeted at the TLB only and not the page walk cache. This works around it by forcing such invalidations to escalate to RIC=2

Re: [bug?] Access was denied by memory protection keys in execute-only address

On Wed, Mar 21, 2018 at 02:53:00PM +0800, Li Wang wrote: >On Wed, Mar 21, 2018 at 5:58 AM, Ram Pai <[1]linux...@us.ibm.com> wrote: > > On Fri, Mar 09, 2018 at 11:43:00AM +0800, Li Wang wrote: > >    On Fri, Mar 9, 2018 at 12:45 AM, Ram Pai > <[1][2]linux...@us.ibm.com> wrote: >

[PATCH 02/19] powerpc/powermac: Mark variable x as unused

Since the value of x is never intended to be read, declare it with gcc attribute as unused. Fix warning treated as error with W=1: arch/powerpc/platforms/powermac/udbg_scc.c:76:9: error: variable ‘x’ set but not used [-Werror=unused-but-set-variable] Signed-off-by: Mathieu Malaterre

[PATCH 07/19] powerpc/powermac: Make some functions static

These functions can all be static, make it so. Fix warnings treated as errors with W=1: arch/powerpc/platforms/powermac/pci.c:1022:6: error: no previous prototype for ‘pmac_pci_fixup_ohci’ [-Werror=missing-prototypes] arch/powerpc/platforms/powermac/pci.c:1057:6: error: no previous prototype