On Thu, Aug 15, 2019 at 02:55:42PM +1000, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> Heads Up: This patch cannot be submitted to Linus's tree, as the affected
> assembler functions have already been converted to C.
>
> When calling flush_(inval_)dcache_range with a size >4GB, we were m
Le 15/08/2019 à 06:10, Alastair D'Silva a écrit :
From: Alastair D'Silva
Similar to commit 22e9c88d486a
("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
this patch converts flush_icache_range() to C, and reimplements the
following functions as wrappers around it:
__flush_dcache
On Wed, 2019-08-14 at 17:47 +0200, Cédric Le Goater wrote:
> Currently, the xmon 'dx' command calls OPAL to dump the XIVE state in
> the OPAL logs and also outputs some of the fields of the internal
> XIVE
> structures in Linux. The OPAL calls can only be done on baremetal
> (PowerNV) and they cras
Le 15/08/2019 à 06:10, Alastair D'Silva a écrit :
From: Alastair D'Silva
When presented with large amounts of memory being hotplugged
(in my test case, ~890GB), the call to flush_dcache_range takes
a while (~50 seconds), triggering RCU stalls.
This patch breaks up the call into 16GB chunks,
Helger, or other parisc folks: can you take a look at this patch
in particular and the series in general? Thanks!
On 15/8/19 3:06 pm, Christopher M. Riedl wrote:> case 'c':
+ if (xmon_is_ro) {
+ printf(xmon_ro_msg);
+ break;
+ }
if (!scanhex(&a)) {
/* clear all breakpoints */
On 15/08/2019 09:30, Jordan Niethe wrote:
> On Wed, 2019-08-14 at 17:47 +0200, Cédric Le Goater wrote:
>> Currently, the xmon 'dx' command calls OPAL to dump the XIVE state in
>> the OPAL logs and also outputs some of the fields of the internal
>> XIVE
>> structures in Linux. The OPAL calls can onl
Add the doorbell mode of MSI-X in EP mode.
Signed-off-by: Xiaowei Bao
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++
drivers/pci/controller/dwc/pcie-designware.h| 14 ++
2 files changed, 28 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-desi
Add multiple PFs support for DWC, different PF have different config space,
we use pf-offset property which get from the DTS to access the different pF
config space.
Signed-off-by: Xiaowei Bao
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 97 +-
drivers/pci/controlle
Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Signed-off-by: Xiaowei Bao
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 7 ---
1 file c
Add compatible strings for ls1088a and ls2088a.
Signed-off-by: Xiaowei Bao
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b/Documentation/devicetree/bin
The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Signed-off-by: Xiaowei Bao
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 28 +++---
1 file changed, 21 in
The layerscape platform use the doorbell way to trigger MSIX
interrupt in EP mode.
Signed-off-by: Xiaowei Bao
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
b/drivers/pci/con
Fix some format issue of the code in EP driver.
Signed-off-by: Xiaowei Bao
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
b/drivers/pci/controller/dwc/pci-layerscape-ep.c
i
Add the pf-offset property for multiple PF.
Signed-off-by: Xiaowei Bao
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-p
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 32 ++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls108
Add LS1088a in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in LS1088a.
Signed-off-by: Xiaowei Bao
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 6e208a
On Thu, Aug 15, 2019 at 10:25:52AM +0100, James Bottomley wrote:
> > which means exporting normally cachable memory to userspace is
> > relatively dangrous due to cache aliasing.
> >
> > But normally cachable memory is only allocated by dma_alloc_coherent
> > on parisc when using the sba_iommu or
On Thu, Aug 15, 2019 at 10:16:33AM +1000, Daniel Axtens wrote:
> Currently, vmalloc space is backed by the early shadow page. This
> means that kasan is incompatible with VMAP_STACK, and it also provides
> a hurdle for architectures that do not have a dedicated module space
> (like powerpc64).
>
>
On Thu, Aug 15, 2019 at 04:37:07PM +0800, Xiaowei Bao wrote:
> Add multiple PFs support for DWC, different PF have different config space,
> we use pf-offset property which get from the DTS to access the different pF
> config space.
Thanks for the patch. I haven't seen a cover letter for this seri
Currently TM signal context tests for GPR, FPR, VMX, and VSX registers
print wrong register numbers (wrongly starting from register 0 instead of
the first register in the non-volatile subset). Besides it the output when
a mismatch happens is poor giving not much information about which context
and
Document all options currently supported by xmon debugger.
Signed-off-by: Gustavo Romero
---
.../admin-guide/kernel-parameters.txt | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/admin-guide/kernel-parameters.txt
b/Documentation/admin-guide/kernel-
Currently some binary files which are generated when tests are compiled
are not ignored by git, so 'git status' catch them.
For copyloops test, fix wrong binary names already in .gitignore. For
ptrace, security, and stringloops tests add missing binary names to the
.gitignore file.
Signed-off-by:
On 14/08/19 10:26 AM, Yinbo Zhu wrote:
> This patch is to add erratum A011334 support in ls1028a 1.0 SoC
>
> Signed-off-by: Yinbo Zhu
Acked-by: Adrian Hunter
> ---
> drivers/mmc/host/sdhci-of-esdhc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
On Thu, Aug 15, 2019 at 04:37:08PM +0800, Xiaowei Bao wrote:
> Add the doorbell mode of MSI-X in EP mode.
>
> Signed-off-by: Xiaowei Bao
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++
> drivers/pci/controller/dwc/pcie-designware.h| 14 ++
> 2 files c
On Thu, Aug 15, 2019 at 04:37:11PM +0800, Xiaowei Bao wrote:
> The different PCIe controller in one board may be have different
> capability of MSI or MSIX, so change the way of getting the MSI
> capability, make it more flexible.
>
> Signed-off-by: Xiaowei Bao
> ---
> drivers/pci/controller/dwc
Hello there,
The CKI Project just found a kernel panic while running the blktests test suite
on stable 5.2.9-rc1[0]. Michael Ellerman requested for this list to be copied
on these ppc64le failures.
We have some logs[1] for these failures and they start with
"ppc64le_host_2_Storage_blktests*".
On Sun, Aug 11, 2019 at 10:05:20AM +0200, Christoph Hellwig wrote:
> We still treat devices without a DMA mask as defaulting to 32-bits for
> both mask, but a few releases ago we've started warning about such
> cases, as they require special cases to work around this sloppyness.
> Add a dma_mask fi
On Wed, Aug 14, 2019 at 6:25 PM Santosh Sivaraj wrote:
>
> Subscribe to the MCE notification and add the physical address which
> generated a memory error to nvdimm bad range.
>
> Signed-off-by: Santosh Sivaraj
> ---
> arch/powerpc/platforms/pseries/papr_scm.c | 65 +++
> 1 f
On Sun, Aug 11, 2019 at 10:05:14AM +0200, Christoph Hellwig wrote:
> Hi all,
>
> this is another attempt to make sure the dma_mask pointer is always
> initialized for platform devices. Not doing so lead to lots of
> boilerplate code, and makes platform devices different from all our
> major busse
On Thu, Aug 15, 2019 at 03:23:18PM +0200, Greg Kroah-Hartman wrote:
> I've taken the first 2 patches for 5.3-final. Given that patch 3 needs
> to be fixed, I'll wait for a respin of these before considering them.
I have a respun version ready, but I'd really like to hear some
comments from usb de
On Wed, Aug 14, 2019 at 04:49:13PM +0100, Robin Murphy wrote:
>> because we have to support platform_device structures that are
>> statically allocated.
>
> This would be a good point to also get rid of the long-standing bodge in
> platform_device_register_full().
platform_device_register_full lo
On Thu, Aug 15, 2019 at 03:03:25PM +0200, Greg Kroah-Hartman wrote:
> > --- a/include/linux/platform_device.h
> > +++ b/include/linux/platform_device.h
> > @@ -24,6 +24,7 @@ struct platform_device {
> > int id;
> > boolid_auto;
> > struct device dev;
> > + u6
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: ba41e1e1ccb9 powerpc/mce: Hookup derror (load/store) UE errors.
The bot has tested the following trees: v5.2.8, v4.19.66.
v5.2.8: Build OK!
v4.19.66: Failed to apply! Possible depe
"Oliver O'Halloran" writes:
> On Wed, Aug 14, 2019 at 6:25 PM Santosh Sivaraj wrote:
>>
>> Subscribe to the MCE notification and add the physical address which
>> generated a memory error to nvdimm bad range.
>>
>> Signed-off-by: Santosh Sivaraj
>> ---
>> arch/powerpc/platforms/pseries/papr_sc
On Thu, Aug 15, 2019 at 03:38:12PM +0200, Christoph Hellwig wrote:
> On Thu, Aug 15, 2019 at 03:03:25PM +0200, Greg Kroah-Hartman wrote:
> > > --- a/include/linux/platform_device.h
> > > +++ b/include/linux/platform_device.h
> > > @@ -24,6 +24,7 @@ struct platform_device {
> > > int i
On Thu, Aug 15, 2019 at 03:25:31PM +0200, Christoph Hellwig wrote:
> On Thu, Aug 15, 2019 at 03:23:18PM +0200, Greg Kroah-Hartman wrote:
> > I've taken the first 2 patches for 5.3-final. Given that patch 3 needs
> > to be fixed, I'll wait for a respin of these before considering them.
>
> I have
On Thu, 2019-08-08 at 19:00 +0300, Christoph Hellwig wrote:
> parisc is the only architecture that sets ARCH_NO_COHERENT_DMA_MMAP
> when an MMU is enabled. AFAIK this is because parisc CPUs use VIVT
> caches,
We're actually VIPT but the same principle applies.
> which means exporting normally c
https://bugzilla.kernel.org/show_bug.cgi?id=204371
--- Comment #26 from Erhard F. (erhar...@mailbox.org) ---
On Wed, 14 Aug 2019 20:33:51 +
bugzilla-dae...@bugzilla.kernel.org wrote:
> https://bugzilla.kernel.org/show_bug.cgi?id=204371
>
>--- Comment #24 from Christophe Leroy (christophe.le.
https://bugzilla.kernel.org/show_bug.cgi?id=204371
--- Comment #27 from Christophe Leroy (christophe.le...@c-s.fr) ---
Can you post the changes you did ?
Did you replace the two kzalloc() by get_zeroed_page() as suggested ?
If so, it looks like you missed one kfree() (in free_bitmap()) to be rep
On 15/08/2019 10:15, Cédric Le Goater wrote:
> On 15/08/2019 09:30, Jordan Niethe wrote:
>> On Wed, 2019-08-14 at 17:47 +0200, Cédric Le Goater wrote:
>>> Currently, the xmon 'dx' command calls OPAL to dump the XIVE state in
>>> the OPAL logs and also outputs some of the fields of the internal
>>>
Does that ring a bell to anyone here ? Thanks
-- Forwarded message -
To:
Hi,
No log only a photo :
https://www.deb-multimedia.org/tests/20190812_143628.jpg
Christian
https://bugzilla.kernel.org/show_bug.cgi?id=204371
--- Comment #28 from Erhard F. (erhar...@mailbox.org) ---
On Thu, 15 Aug 2019 16:45:11 +
bugzilla-dae...@bugzilla.kernel.org wrote:
> https://bugzilla.kernel.org/show_bug.cgi?id=204371
>
> --- Comment #27 from Christophe Leroy (christophe.le
https://bugzilla.kernel.org/show_bug.cgi?id=204371
--- Comment #29 from Christophe Leroy (christophe.le...@c-s.fr) ---
Looks good. Does it work better ?
--
You are receiving this mail because:
You are on the CC list for the bug.
Le 15/08/2019 à 19:05, Mathieu Malaterre a écrit :
Does that ring a bell to anyone here ? Thanks
Apparently that's 5.2.0, not 5.2.7
Christophe
-- Forwarded message -
To:
Hi,
No log only a photo :
https://www.deb-multimedia.org/tests/20190812_143628.jpg
Christian
-
Le 15/08/2019 à 19:48, Christian Marillat a écrit :
On 15 août 2019 19:29, christophe leroy wrote:
Le 15/08/2019 à 19:05, Mathieu Malaterre a écrit :
Does that ring a bell to anyone here ? Thanks
Apparently that's 5.2.0, not 5.2.7
Yes, 5.2.7 is the Debian package version. Sorry for the
On Thu, Aug 15, 2019 at 06:54:39AM -0700, Rob Clark wrote:
> On Wed, Aug 14, 2019 at 11:51 PM Christoph Hellwig wrote:
> >
> > As said before I don't think these low-level helpers are the
> > right API to export, but even if they did you'd just cover a tiny
> > subset of the architectures.
>
> Ar
https://bugzilla.kernel.org/show_bug.cgi?id=204371
--- Comment #30 from Erhard F. (erhar...@mailbox.org) ---
On Thu, 15 Aug 2019 17:11:36 +
bugzilla-dae...@bugzilla.kernel.org wrote:
> https://bugzilla.kernel.org/show_bug.cgi?id=204371
>
> --- Comment #29 from Christophe Leroy (christophe.le
On Wed, Aug 14, 2019 at 10:49:18PM +0200, Arnd Bergmann wrote:
> All watchdog drivers implement the same set of ioctl commands, and
> fortunately all of them are compatible between 32-bit and 64-bit
> architectures.
>
> Modern drivers always go through drivers/watchdog/wdt.c as an abstraction
> la
Am 15.08.19 um 19:53 schrieb Christoph Hellwig:
> On Thu, Aug 15, 2019 at 06:54:39AM -0700, Rob Clark wrote:
>> On Wed, Aug 14, 2019 at 11:51 PM Christoph Hellwig wrote:
>>> As said before I don't think these low-level helpers are the
>>> right API to export, but even if they did you'd just cover
On Thu, Aug 15, 2019 at 06:21:00PM +, Koenig, Christian wrote:
> > (2) Add support for DMA_ATTR_NO_KERNEL_MAPPING to this new API instead
> > of dma_alloc_attrs. The initial difference with that flag is just
> > that we allow highmem, but in the future we could also unmap this
>
https://bugzilla.kernel.org/show_bug.cgi?id=204371
--- Comment #31 from Christophe Leroy (christophe.le...@c-s.fr) ---
Problem 1: test_add_free_space_entry() contains a kzalloc() to allocate a
bitmap. That's the problem.
Problem 2: btrfs_free_dummy_fs_info() has 3 kfree(). Need to know which one
On Thu, Aug 15, 2019 at 06:48:39PM +, Koenig, Christian wrote:
> Well, for the graphics case I absolutely need to keep the linear kernel
> mapping. Because for certain use cases the memory is accessed by the kernel
> all the time as well.
Then don't set DMA_ATTR_NO_KERNEL_MAPPING. At least
On Tue, Aug 13, 2019 at 9:22 PM Dan Williams wrote:
>
> Hi Aneesh, logic looks correct but there are some cleanups I'd like to
> see and a lead-in patch that I attached.
>
> I've started prefixing nvdimm patches with:
>
> libnvdimm/$component:
>
> ...since this patch mostly impacts the pmem dr
On Thu, 15 Aug 2019, Christoph Hellwig wrote:
> On Thu, Aug 15, 2019 at 03:23:18PM +0200, Greg Kroah-Hartman wrote:
> > I've taken the first 2 patches for 5.3-final. Given that patch 3 needs
> > to be fixed, I'll wait for a respin of these before considering them.
>
> I have a respun version rea
On Fri, Aug 9, 2019 at 12:45 AM Aneesh Kumar K.V
wrote:
>
> Use PAGE_SIZE instead of SZ_4K and sizeof(struct page) instead of 64.
> If we have a kernel built with different struct page size the previous
> patch should handle marking the namespace disabled.
Each of these changes carry independent
On Wed, Aug 14, 2019 at 11:51 PM Christoph Hellwig wrote:
>
> As said before I don't think these low-level helpers are the
> right API to export, but even if they did you'd just cover a tiny
> subset of the architectures.
Are you thinking instead something like:
void dma_sync_sg_for_{cpu,device}
On 15 août 2019 19:05, Mathieu Malaterre wrote:
> Does that ring a bell to anyone here ? Thanks
Din't reply to all. Second reply :
Nothing. Fans turn 100% after 1 or 2 minutes.
Christian
On 15 août 2019 19:29, christophe leroy wrote:
> Le 15/08/2019 à 19:05, Mathieu Malaterre a écrit :
>> Does that ring a bell to anyone here ? Thanks
>
> Apparently that's 5.2.0, not 5.2.7
Yes, 5.2.7 is the Debian package version. Sorry for the mistake.
Christian
Sorry if the style is messed up, replying from my phone.
Am 15.08.2019 20:27 schrieb Christoph Hellwig :
On Thu, Aug 15, 2019 at 06:21:00PM +, Koenig, Christian wrote:
> > (2) Add support for DMA_ATTR_NO_KERNEL_MAPPING to this new API instead
> > of dma_alloc_attrs. The initial differ
On Wed, Aug 14, 2019 at 2:26 AM Yinbo Zhu wrote:
>
> Adding compatible string "ls1028a-dcfg" to initialize guts driver
> for ls1028 and SoC die attribute definition for LS1028A
>
> Signed-off-by: Yinbo Zhu
Applied for next.
> ---
> drivers/soc/fsl/guts.c | 6 ++
> 1 file changed, 6 inserti
On Thu, Aug 1, 2019 at 3:20 PM Roy Pledge wrote:
>
> Most DPAA1 devices do not support a soft reset which is an issue if
> Kexec starts a new kernel. This patch series allows Kexec to function
> by detecting that the QBMan device was previously initialized.
>
> The patches fix some issues with dev
Michael Ellerman writes:
> Thiago Jung Bauermann writes:
>> Michael Ellerman writes:
>>> Thiago Jung Bauermann writes:
From: Ryan Grimm
User space might want to know it's running in a secure VM. It can't do
a mfmsr because mfmsr is a privileged instruction.
The sol
Michael Ellerman writes:
> Thiago Jung Bauermann writes:
>> Michael Ellerman writes:
>>> Thiago Jung Bauermann writes:
From: Anshuman Khandual
LPPACA structures need to be shared with the host. Hence they need to be in
shared memory. Instead of allocating individual chun
Greg Kroah-Hartman writes:
> On Thu, Aug 15, 2019 at 02:55:42PM +1000, Alastair D'Silva wrote:
>> From: Alastair D'Silva
>>
>> Heads Up: This patch cannot be submitted to Linus's tree, as the affected
>> assembler functions have already been converted to C.
That was done in upstream commit:
22
On Thu, 2019-08-15 at 09:29 +0200, christophe leroy wrote:
>
> Le 15/08/2019 à 06:10, Alastair D'Silva a écrit :
> > From: Alastair D'Silva
> >
> > Similar to commit 22e9c88d486a
> > ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
> > this patch converts flush_icache_range() to C,
On Thu, 2019-08-15 at 09:36 +0200, christophe leroy wrote:
>
> Le 15/08/2019 à 06:10, Alastair D'Silva a écrit :
> > From: Alastair D'Silva
> >
> > When presented with large amounts of memory being hotplugged
> > (in my test case, ~890GB), the call to flush_dcache_range takes
> > a while (~50 se
On 14/08/19 10:45 PM, Mahesh J Salgaonkar wrote:
> On 2019-07-16 17:04:08 Tue, Hari Bathini wrote:
>> From: Hari Bathini
>>
>> Firmware provides architected register state data at the time of crash.
>> Process this data and build CPU notes to append to ELF core.
>>
>> Signed-off-by: Hari Bathin
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月15日 19:32
> To: Xiaowei Bao
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.com; a
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月15日 19:54
> To: Xiaowei Bao
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.com; a
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月15日 20:51
> To: Xiaowei Bao
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.com; a
Since the RFC I accounted for feedback, and also made the patch more
complete so we can actually boot and run a 64s/radix kernel without
using tlbie at all.
KVM and bare metal hash are harder to support. Bare metal hash because
it does some TLB invation with interrupts disabled (can't use IPIs).
I
This was an awkward interface that didn't quite suit bare metal boot,
because the host page table base is stored into the partition table at
a different place than the process table base, and the TLB flushing is
unnecessary at boot with the MMU off, provided all CPUs invalidate
all their translatio
Rather than sprinkle various translation structure invalidations
around different places in early boot, have each CPU flush everything
from its local translation structures before enabling its MMU.
Radix guests can execute tlbie(l), so have them tlbiel_all in the same
place as radix host does.
Si
Introduce two options to control the use of the tlbie instruction. A
boot time option which completely disables the kernel using the
instruction, this is currently incompatible with HASH MMU, KVM, and
coherent accelerators.
And a debugfs option can be switched at runtime and avoids using tlbie
for
Christophe Leroy writes:
> Le 07/08/2019 à 01:38, Daniel Axtens a écrit :
>> Building on the work of Christophe, Aneesh and Balbir, I've ported
>> KASAN to 64-bit Book3S kernels running on the Radix MMU.
>>
>> It builds on top Christophe's work on 32bit. It also builds on my
>> generic KASAN_VMA
Hi Xiaowei,
> -Original Message-
> From: Xiaowei Bao
> Sent: 2019年8月6日 14:16
> To: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.com; a...@arndb.de; gre...@linuxfoundation.org;
> M.h. Lian ; Mingkai Hu
Hi all,
Here is v5, with a complete rewrite of the commit message for patch 1, and the
inclusion of three patches from another set which are based on this set
(previously titled "EEH fixes 4").
Cover letter:
This patch set adds support for EEH recovery of hot plugged devices on pSeries
machines.
The pcibios_init() function for PowerPC 64 currently calls
pci_bus_add_devices() before pcibios_resource_survey(). This means
that at boot time, when the pcibios_bus_add_device() hooks are called
by pci_bus_add_devices(), device resources have not been allocated and
they are unable to perform EEH s
The EEH address cache is currently initialized and populated by a
single function: eeh_addr_cache_build(). While the initial population
of the cache can only be done once resources are allocated,
initialization (just setting up a spinlock) could be done much
earlier.
So move the initialization st
The EEH_DEV_NO_HANDLER flag is used by the EEH system to prevent the
use of driver callbacks in drivers that have been bound part way
through the recovery process. This is necessary to prevent later stage
handlers from being called when the earlier stage handlers haven't,
which can be confusing for
From: Oliver O'Halloran
Preparation for removing pci_dn from the powernv EEH code. The only
thing we really use pci_dn for is to get the bdfn of the device for
config space accesses, so adding that information to eeh_dev reduces
the need to carry around the pci_dn.
Signed-off-by: Oliver O'Hallor
Simplify some needlessly complicated boolean logic in
eeh_add_to_parent_pe().
Signed-off-by: Sam Bobroff
---
v5 * New in this version.
arch/powerpc/kernel/eeh_pe.c | 52 +++-
1 file changed, 27 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/kernel/eeh_
Now that struct eeh_dev includes the BDFN of it's PCI device, make use
of it to replace eeh_edev_info() with a set of dev_dbg()-style macros
that only need a struct edev.
With the BDFN available without the struct pci_dev, eeh_pci_name() is
now unnecessary, so remove it.
While only the "info" lev
Now that EEH support for all devices (on PowerNV and pSeries) is
provided by the pcibios bus add device hooks, eeh_probe_devices() and
eeh_addr_cache_build() are redundant and can be removed.
Move the EEH enabled message into it's own function so that it can be
called from multiple places.
Note t
If a PCI device is removed during eeh_pe_report_edev(), between the
calls to device_lock() and device_unlock(), edev->pdev will change and
cause a crash as the wrong mutex is released.
To correct this, hold the PCI rescan/remove lock while taking a copy
of edev->pdev and performing a get_device()
Also remove useless comment.
Signed-off-by: Sam Bobroff
Reviewed-by: Alexey Kardashevskiy
---
arch/powerpc/kernel/eeh.c| 2 +-
arch/powerpc/platforms/powernv/eeh-powernv.c | 14
arch/powerpc/platforms/pseries/eeh_pseries.c | 23 +++-
3 files cha
On PowerNV and pSeries, devices currently acquire EEH support from
several different places: Boot-time devices from eeh_probe_devices()
and eeh_addr_cache_build(), Virtual Function devices from the pcibios
bus add device hooks and hot plugged devices from pci_hp_add_devices()
(with other platforms
Convert existing messages, where appropriate, to use the eeh_edev_*
logging macros.
The only effect should be minor adjustments to the log messages, apart
from:
- A new message in pseries_eeh_probe() "Probing device" to match the
powernv case.
- The "Probing device" message in pnv_eeh_probe() is
There are no users of the early-out return value from
eeh_pe_dev_traverse(), so remove it.
Signed-off-by: Sam Bobroff
---
v5 * New in this version.
arch/powerpc/include/asm/eeh.h | 6 +++---
arch/powerpc/kernel/eeh.c| 16 +---
arch/powerpc/kernel/eeh_driver.c | 26 +++
On 2019-07-16 17:04:16 Tue, Hari Bathini wrote:
> Add a new kernel config option, CONFIG_PRESERVE_FA_DUMP that ensures
> that crash data, from previously crash'ed kernel, is preserved. This
> helps in cases where FADump is not enabled but the subsequent memory
> preserving kernel boot is likely to
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power
source of modules during system suspend and resume procedure.
Thus, AUDMUX needs to save all the values of registers before the
system suspend and restore them after the system resume.
Signed-off-by: Shengjiu Wang
---
sound/soc/fs
Only BOOK3S and FSL_BOOK3E have a usefull update_mmu_cache().
For the others, just define it static inline.
In the meantime, simplify the FSL_BOOK3E related ifdef as
book3e_hugetlb_preload() only exists when CONFIG_PPC_FSL_BOOK3E
is selected.
Signed-off-by: Christophe Leroy
---
arch/powerpc/in
Move FSL_BOOK3E version of update_mmu_cache() at the same
place as book3e_hugetlb_preload() as update_mmu_cache() is
the only user of book3e_hugetlb_preload().
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/hugetlb.h | 3 ---
arch/powerpc/mm/mem.c |
update_mmu_cache() is only for BOOK3S, and can be simplified
for BOOK3S32.
Move it out of mem.c into respective BOOK3S32 and BOOK3S64
files containing hash utils.
BOOK3S64 version of hash_preload() is only used locally,
declare it static.
Remove the radix_enabled() stuff in BOOK3S32 version.
Si
On BOOK3S32, hash_preload() neither use is_exec nor trap,
so drop those parameters and simplify update_mmu_cached().
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s32/mmu.c | 29 +++--
arch/powerpc/mm/mmu_decl.h | 3 +--
arch/powerpc/mm/pgtable_32.c | 2
On powerpc 603, there is no hash table so get out of
update_mmu_cache() early.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s32/mmu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index 3a62bf99f93f..c20269be79ec
On 2019-07-16 17:04:38 Tue, Hari Bathini wrote:
> If not all kernel boot memory regions are registered for MPIPL before
> system crashes, try processing the partial crashdump but warn the user
> before proceeding.
>
> Signed-off-by: Hari Bathini
> ---
> arch/powerpc/platforms/powernv/opal-fadump
Hi all,
this is another attempt to make sure the dma_mask pointer is always
initialized for platform devices. Not doing so lead to lots of
boilerplate code, and makes platform devices different from all our
major busses like PCI where we always set up a dma_mask. In the long
run this should also
On 15 août 2019 19:50, christophe leroy wrote:
> Le 15/08/2019 à 19:48, Christian Marillat a écrit :
>> On 15 août 2019 19:29, christophe leroy wrote:
>>
>>> Le 15/08/2019 à 19:05, Mathieu Malaterre a écrit :
Does that ring a bell to anyone here ? Thanks
>>>
>>> Apparently that's 5.2.0, not
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