On Wed, Nov 27, 2019 at 08:56:25AM +0200, Mike Rapoport wrote:
> On Tue, Nov 26, 2019 at 05:40:26PM +0100, Christoph Hellwig wrote:
> > On Tue, Nov 26, 2019 at 12:26:38PM +0100, Christian Zigotzky wrote:
> > > Hello Christoph,
> > >
> > > The PCI TV card works with your patch! I was able to patch
There are two asrc module in imx8qm & imx8qxp, each module has
different clock configuration, and the DMA type is EDMA.
So in this patch, we define the new clocks, refine the clock map,
and include struct fsl_asrc_soc_data for different soc usage.
The EDMA channel is fixed with each dma request,
Hi
On Mon, Dec 2, 2019 at 8:58 PM Fabio Estevam wrote:
>
> On Mon, Dec 2, 2019 at 8:56 AM Shengjiu Wang wrote:
>
> > - - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc".
> > + - compatible : Contains "fsl,imx35-asrc", "fsl,imx53-asrc",
> > +
This commit introduces and leverages the Self save API which OPAL now
supports.
Add the new Self Save OPAL API call in the list of OPAL calls.
Implement the self saving of the SPRs based on the support populated
while respecting it's preferences.
This implementation allows mixing of support for
Add compatible string "fsl,imx8qm-asrc" for imx8qm platform,
"fsl,imx8qxp-asrc" for imx8qxp platform.
There are two asrc modules in imx8qm & imx8qxp, the clock mapping is
different for each other, so add new property "fsl,asrc-clk-map"
to distinguish them.
Signed-off-by: Shengjiu Wang
---
I think we have to wait to Roland’s test results with his SCSI PCI card.
Christian
Sent from my iPhone
> On 4. Dec 2019, at 09:56, Christoph Hellwig wrote:
>
>> On Wed, Nov 27, 2019 at 08:56:25AM +0200, Mike Rapoport wrote:
>>> On Tue, Nov 26, 2019 at 05:40:26PM +0100, Christoph Hellwig
The recent commit 81d2c6f81996 ("kasan: support instrumented bitops
combined with generic bitops"), split the KASAN instrumented bitops
into separate headers for atomic, non-atomic and locking operations.
This was done to allow arches to include just the instrumented bitops
they need, while also
Parse the device tree for nodes self-save, self-restore and populate
support for the preferred SPRs based what was advertised by the device
tree.
Signed-off-by: Pratik Rajesh Sampat
---
arch/powerpc/platforms/powernv/idle.c | 104 ++
1 file changed, 104 insertions(+)
Currently the stop-api supports a mechanism called as self-restore
which allows us to restore the values of certain SPRs on wakeup from a
deep-stop state to a desired value. To use this, the Kernel makes an
OPAL call passing the PIR of the CPU, the SPR number and the value to
which the SPR should
Define a bitmask interface to determine support for the Self Restore,
Self Save or both.
Also define an interface to determine the preference of that SPR to
be strictly saved or restored or encapsulated with an order of preference.
The preference bitmask is shown as below:
On Wed, 2019-12-04 at 05:29:09 UTC, "Aneesh Kumar K.V" wrote:
> This patch fix the below kernel crash.
>
> BUG: Unable to handle kernel data access on read at 0xc0038000
> Faulting instruction address: 0xc008b6f0
> cpu 0x5: Vector: 300 (Data Access) at [c000d8587790]
>
On Tue, 3 Dec 2019 17:36:42 +0100
Cédric Le Goater wrote:
> The PCI INTx interrupts and other LSI interrupts are handled differently
> under a sPAPR platform. When the interrupt source characteristics are
> queried, the hypervisor returns an H_INT_ESB flag to inform the OS
> that it should be
Hi Kamalesh,
On Tue, Dec 03, 2019 at 07:07:53PM +0530, Kamalesh Babulal wrote:
> On 11/27/19 5:31 PM, Gautham R. Shenoy wrote:
> > From: "Gautham R. Shenoy"
> >
> > On Pseries LPARs, to calculate utilization, we need to know the
> > [S]PURR ticks when the CPUs were busy or idle.
> >
> > The
Commit 01c9348c7620ec65
powerpc: Use hardware RNG for arch_get_random_seed_* not arch_get_random_*
updated arch_get_random_[int|long]() to be NOPs, and moved the hardware
RNG backing to arch_get_random_seed_[int|long]() instead. However, it
failed to take into account that
On Tue, 2019-12-03 at 16:36:42 UTC, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= wrote:
> The PCI INTx interrupts and other LSI interrupts are handled differently
> under a sPAPR platform. When the interrupt source characteristics are
> queried, the hypervisor returns an H_INT_ESB flag to inform the OS
>
With the static key shared processor available, is_shared_processor()
can return without having to query the lppaca structure.
Signed-off-by: Srikar Dronamraju
---
arch/powerpc/include/asm/spinlock.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
On Fri, 2019-11-29 at 14:26:41 UTC, Christophe Leroy wrote:
> When enabling CONFIG_RELOCATABLE and CONFIG_KASAN on FSL_BOOKE,
> the kernel doesn't boot.
>
> relocate_init() requires KASAN early shadow area to be set up because
> it needs access to the device tree through generic functions.
>
>
On Mon, 2019-12-02 at 07:57:29 UTC, Christophe Leroy wrote:
> From: Vincenzo Frascino
>
> clock_getres in the vDSO library has to preserve the same behaviour
> of posix_get_hrtimer_res().
>
> In particular, posix_get_hrtimer_res() does:
> sec = 0;
> ns = hrtimer_resolution;
> and
>
> Fixes: 076265907cf9 ("powerpc: Chunk calls to flush_dcache_range in
> arch_*_memory")
> Reported-by: Sachin Sant
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/mem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
It took a while to setup environment on a
- Original Message -
> Please try the patch below:
I ran reproducer for 18 hours on 2 systems were it previously reproduced,
there were no crashes / SIGBUS.
* Srikar Dronamraju [2019-12-04 19:14:58]:
>
>
> # perf stat -a -r 5 ./schbench
> v5.4 v5.4 + patch
> Latency percentiles (usec) Latency percentiles (usec)
> 49.th: 47 50.th: 33
>
From: Mike Rapoport
Some powerpc platforms (e.g. 85xx) limit DMA-able memory way below 4G. If a
system has more physical memory than this limit, the swiotlb buffer is not
addressable because it is allocated from memblock using top-down mode.
Force memblock to bottom-up mode before calling
With commit 247f2f6f3c70 ("sched/core: Don't schedule threads on pre-empted
vCPUs"), scheduler avoids preempted vCPUs to schedule tasks on wakeup.
This leads to wrong choice of CPU, which in-turn leads to larger wakeup
latencies. Eventually, it leads to performance regression in latency
sensitive
On Wed, Dec 04, 2019 at 02:35:24PM +0200, Mike Rapoport wrote:
> From: Mike Rapoport
>
> Some powerpc platforms (e.g. 85xx) limit DMA-able memory way below 4G. If a
> system has more physical memory than this limit, the swiotlb buffer is not
> addressable because it is allocated from memblock
From: Wen Yang
[ Upstream commit 40752b3eae29f8ca2378e978a02bd6dbeeb06d16 ]
This patch fixes potential double frees if register_hdlc_device() fails.
Signed-off-by: Wen Yang
Reviewed-by: Peng Hao
CC: Zhao Qiang
CC: "David S. Miller"
CC: net...@vger.kernel.org
CC:
From: Wen Yang
[ Upstream commit 40752b3eae29f8ca2378e978a02bd6dbeeb06d16 ]
This patch fixes potential double frees if register_hdlc_device() fails.
Signed-off-by: Wen Yang
Reviewed-by: Peng Hao
CC: Zhao Qiang
CC: "David S. Miller"
CC: net...@vger.kernel.org
CC:
With the static key shared processor available, is_shared_processor()
can return without having to query the lppaca structure.
Signed-off-by: Srikar Dronamraju
---
Changelog v1->v2:
Now that we no more refer to lppaca, remove the comment.
arch/powerpc/include/asm/spinlock.h | 9 ++---
1
On Sun, 2019-12-01 at 22:45 -0800, Ram Pai wrote:
> @@ -206,8 +224,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table
> *tbl, long tcenum,
> * from iommu_alloc{,_sg}()
> */
> if (!tcep) {
> - tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
> -
On Thu, 5 Dec 2019 00:30:56 +1100 (AEDT)
Michael Ellerman wrote:
> On Tue, 2019-12-03 at 16:36:42 UTC, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?=
> wrote:
> > The PCI INTx interrupts and other LSI interrupts are handled differently
> > under a sPAPR platform. When the interrupt source
In case we have to migrate a ballon page to a newpage of another zone, the
managed page count of both zones is wrong. Paired with memory offlining
(which will adjust the managed page count), we can trigger kernel crashes
and all kinds of different symptoms.
Fix it by properly adjusting the
On 05/12/2019 07:42, Ram Pai wrote:
> On Wed, Dec 04, 2019 at 02:36:18PM +1100, David Gibson wrote:
>> On Wed, Dec 04, 2019 at 12:08:09PM +1100, Alexey Kardashevskiy wrote:
>>>
>>>
>>> On 04/12/2019 11:49, Ram Pai wrote:
On Wed, Dec 04, 2019 at 11:04:04AM +1100, Alexey Kardashevskiy wrote:
"Gautham R. Shenoy" writes:
> +
> +What:/sys/devices/system/cpu/cpuX/idle_purr
> +Date:Nov 2019
> +Contact: Linux for PowerPC mailing list
> +Description: PURR ticks for cpuX when it was idle.
> +
> + This sysfs interface exposes the number of PURR
On Wed, Dec 04, 2019 at 02:36:18PM +1100, David Gibson wrote:
> On Wed, Dec 04, 2019 at 12:08:09PM +1100, Alexey Kardashevskiy wrote:
> >
> >
> > On 04/12/2019 11:49, Ram Pai wrote:
> > > On Wed, Dec 04, 2019 at 11:04:04AM +1100, Alexey Kardashevskiy wrote:
> > >>
> > >>
> > >> On 04/12/2019
Forgot to rename the subject to
"powerpc/pseries/cmm: fix managed page counts when migrating pages
between zones"
If I don't have to resend, would be great if that could be adjusted when
applying.
--
Thanks,
David / dhildenb
On 12/4/19 8:44 AM, Srikar Dronamraju wrote:
> With commit 247f2f6f3c70 ("sched/core: Don't schedule threads on pre-empted
> vCPUs"), scheduler avoids preempted vCPUs to schedule tasks on wakeup.
> This leads to wrong choice of CPU, which in-turn leads to larger wakeup
> latencies. Eventually, it
"Gautham R. Shenoy" writes:
> @@ -1067,6 +1097,8 @@ static int __init topology_init(void)
> register_cpu(c, cpu);
>
> device_create_file(>dev, _attr_physical_id);
> + if (firmware_has_feature(FW_FEATURE_SPLPAR))
> +
Commit a25bd72badfa ("powerpc/mm/radix: Workaround prefetch issue with
KVM") introduced a number of workarounds as coming out of a guest with
the mmu enabled would make the cpu would start running in hypervisor
state with the PID value from the guest. The cpu will then start
prefetching for the
Greg Kurz writes:
> On Thu, 5 Dec 2019 00:30:56 +1100 (AEDT)
> Michael Ellerman wrote:
>> On Tue, 2019-12-03 at 16:36:42 UTC, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?=
>> wrote:
>> > The PCI INTx interrupts and other LSI interrupts are handled differently
>> > under a sPAPR platform. When the
"Gautham R. Shenoy" writes:
> diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
> index a36fd05..708ec68 100644
> --- a/arch/powerpc/kernel/idle.c
> +++ b/arch/powerpc/kernel/idle.c
> @@ -33,6 +33,8 @@
> unsigned long cpuidle_disable = IDLE_NO_OVERRIDE;
>
On Wed, Dec 04, 2019 at 03:26:50PM -0300, Leonardo Bras wrote:
> On Sun, 2019-12-01 at 22:45 -0800, Ram Pai wrote:
> > @@ -206,8 +224,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table
> > *tbl, long tcenum,
> > * from iommu_alloc{,_sg}()
> > */
> > if (!tcep) {
"Gautham R. Shenoy" writes:
> From: "Gautham R. Shenoy"
>
> On PSeries LPARs, the data centers planners desire a more accurate
> view of system utilization per resource such as CPU to plan the system
> capacity requirements better. Such accuracy can be obtained by reading
> PURR/SPURR registers
On Tue, Dec 03, 2019 at 07:13:03PM +0800, Chuhong Yuan wrote:
> The driver forgets to call pm_runtime_disable in probe failure
> and remove.
> Add the missed calls to fix it.
>
> Signed-off-by: Chuhong Yuan
Acked-by: Nicolin Chen
Thanks
> ---
> sound/soc/fsl/fsl_audmix.c | 9 -
> 1
David Hildenbrand writes:
> Forgot to rename the subject to
>
> "powerpc/pseries/cmm: fix managed page counts when migrating pages
> between zones"
>
> If I don't have to resend, would be great if that could be adjusted when
> applying.
I can do that.
I'm inclined to wait until the
On Thu, Nov 28, 2019 at 11:38:02PM +0100, Michael Walle wrote:
> The LS1028A SoC uses the same interrupt line for adjacent SAIs. Use
> IRQF_SHARED to be able to use these SAIs simultaneously.
>
> Signed-off-by: Michael Walle
Acked-by: Nicolin Chen
Thanks
> ---
> sound/soc/fsl/fsl_sai.c | 3
On Tue, 2019-12-03 at 14:46 +1100, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> The read error log command extracts information from the controller's
> internal error log.
>
> This patch exposes this information in 2 ways:
> - During probe, if an error occurs & a log is available, print
Many of the performance moniroting unit (PMU) SPRs are
exposed in the sysfs. "perf" API is the primary interface to program
PMU and collect counter data in the system. So expose these
PMU SPRs in the absence of CONFIG_PERF_EVENTS.
Patch adds a new CONFIG option 'CONFIG_PMU_SYSFS'. The new config
On Thu, Dec 05, 2019 at 09:26:14AM +1100, Alexey Kardashevskiy wrote:
>
>
> On 05/12/2019 07:42, Ram Pai wrote:
> > On Wed, Dec 04, 2019 at 02:36:18PM +1100, David Gibson wrote:
> >> On Wed, Dec 04, 2019 at 12:08:09PM +1100, Alexey Kardashevskiy wrote:
> >>>
> >>>
> >>> On 04/12/2019 11:49, Ram
Hi Srikar,
On Wed, Dec 04, 2019 at 07:14:58PM +0530, Srikar Dronamraju wrote:
> With commit 247f2f6f3c70 ("sched/core: Don't schedule threads on pre-empted
> vCPUs"), scheduler avoids preempted vCPUs to schedule tasks on wakeup.
> This leads to wrong choice of CPU, which in-turn leads to larger
> Am 05.12.2019 um 03:59 schrieb Michael Ellerman :
>
> David Hildenbrand writes:
>> Forgot to rename the subject to
>>
>> "powerpc/pseries/cmm: fix managed page counts when migrating pages
>> between zones"
>>
>> If I don't have to resend, would be great if that could be adjusted when
>>
Le 05/12/2019 à 06:25, Kajol Jain a écrit :
Many of the performance moniroting unit (PMU) SPRs are
exposed in the sysfs. "perf" API is the primary interface to program
PMU and collect counter data in the system. So expose these
PMU SPRs in the absence of CONFIG_PERF_EVENTS.
Patch adds a new
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