[powerpc:next] BUILD SUCCESS 9a77c4a0a12597c661be374b8d566516c0341570

2020-07-21 Thread kernel test robot
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next branch HEAD: 9a77c4a0a12597c661be374b8d566516c0341570 powerpc/prom: Enable Radix GTSE in cpu pa-features elapsed time: 1700m configs tested: 117 configs skipped: 4 The following configs have been built

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Alex Ghiti
Let's try to make progress here: I add linux-mm in CC to get feedback on this patch as it blocks sv48 support too. Alex Le 7/9/20 à 7:11 AM, Alex Ghiti a écrit : Hi Palmer, Le 7/9/20 à 1:05 AM, Palmer Dabbelt a écrit : On Sun, 07 Jun 2020 00:59:46 PDT (-0700), a...@ghiti.fr wrote: This is

Re: [PATCH v6] ima: move APPRAISE_BOOTPARAM dependency on ARCH_POLICY to runtime

2020-07-21 Thread Mimi Zohar
On Mon, 2020-07-20 at 12:38 -0300, Bruno Meneguele wrote: > On Mon, Jul 20, 2020 at 10:56:55AM -0400, Mimi Zohar wrote: > > On Mon, 2020-07-20 at 10:40 -0400, Nayna wrote: > > > On 7/13/20 12:48 PM, Bruno Meneguele wrote: > > > > The IMA_APPRAISE_BOOTPARAM config allows enabling different > > > >

Re: [PATCH v4 6/7] powerpc/pseries/iommu: Make use of DDW even if it does not map the partition

2020-07-21 Thread Leonardo Bras
On Thu, 2020-07-16 at 04:16 -0300, Leonardo Bras wrote: > +static void iommu_pseries_table_update(struct pci_dev *dev, > + struct device_node *pdn) > +{ > + const struct dynamic_dma_window_prop *ddw; > + struct pci_dn *pci; > + int len; > + >

Re: [PATCH v2 2/2] KVM: PPC: Book3S HV: rework secure mem slot dropping

2020-07-21 Thread Ram Pai
On Tue, Jul 21, 2020 at 12:42:02PM +0200, Laurent Dufour wrote: > When a secure memslot is dropped, all the pages backed in the secure device > (aka really backed by secure memory by the Ultravisor) should be paged out > to a normal page. Previously, this was achieved by triggering the page >

Re: [PATCH v6] ima: move APPRAISE_BOOTPARAM dependency on ARCH_POLICY to runtime

2020-07-21 Thread Bruno Meneguele
On Tue, Jul 21, 2020 at 01:26:16PM -0400, Mimi Zohar wrote: > On Mon, 2020-07-20 at 12:38 -0300, Bruno Meneguele wrote: > > On Mon, Jul 20, 2020 at 10:56:55AM -0400, Mimi Zohar wrote: > > > On Mon, 2020-07-20 at 10:40 -0400, Nayna wrote: > > > > On 7/13/20 12:48 PM, Bruno Meneguele wrote: > > > >

[powerpc:next-test] BUILD REGRESSION 08b8bb849948ff5e2305d1115ce8bbdd55364a70

2020-07-21 Thread kernel test robot
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next-test branch HEAD: 08b8bb849948ff5e2305d1115ce8bbdd55364a70 powerpc test_emulate_step: move extern declaration to sstep.h Error/Warning in current branch: arch/powerpc/include/asm/ppc-opcode.h:277:22: error:

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Palmer Dabbelt
On Tue, 21 Jul 2020 11:36:10 PDT (-0700), a...@ghiti.fr wrote: Let's try to make progress here: I add linux-mm in CC to get feedback on this patch as it blocks sv48 support too. Sorry for being slow here. I haven't replied because I hadn't really fleshed out the design yet, but just so

Re: [PATCH v2 1/2] KVM: PPC: Book3S HV: move kvmppc_svm_page_out up

2020-07-21 Thread Ram Pai
On Tue, Jul 21, 2020 at 12:42:01PM +0200, Laurent Dufour wrote: > kvmppc_svm_page_out() will need to be called by kvmppc_uvmem_drop_pages() > so move it upper in this file. > > Furthermore it will be interesting to call this function when already > holding the kvm->arch.uvmem_lock, so prefix the

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Benjamin Herrenschmidt
On Tue, 2020-07-21 at 14:36 -0400, Alex Ghiti wrote: > > > I guess I don't understand why this is necessary at all. > > > Specifically: why > > > can't we just relocate the kernel within the linear map? That would > > > let the > > > bootloader put the kernel wherever it wants, modulo the

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Benjamin Herrenschmidt
On Tue, 2020-07-21 at 12:05 -0700, Palmer Dabbelt wrote: > > * We waste vmalloc space on 32-bit systems, where there isn't a lot of it. > * On 64-bit systems the VA space around the kernel is precious because it's > the > only place we can place text (modules, BPF, whatever). Why ? Branch

Re: [v3 01/15] powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers

2020-07-21 Thread Athira Rajeev
> On 21-Jul-2020, at 9:12 AM, Jordan Niethe wrote: > > On Sat, Jul 18, 2020 at 12:48 AM Athira Rajeev > mailto:atraj...@linux.vnet.ibm.com>> wrote: >> >> core-book3s currently uses array to store the MMCR registers as part >> of per-cpu `cpu_hw_events`. This patch does a clean up to use

Re: [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR

2020-07-21 Thread Athira Rajeev
> On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote: > > On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote: >> Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers >> in a flat array in order: mmcr0, mmcr1, mmcra, mmcr2, mmcrs >> Split this to give mmcra and mmcrs its

Re: [PATCH v4 07/12] ppc64/kexec_file: add support to relocate purgatory

2020-07-21 Thread Michael Ellerman
Hari Bathini writes: > Right now purgatory implementation is only minimal. But if purgatory > code is to be enhanced to copy memory to the backup region and verify > sha256 digest, relocations may have to be applied to the purgatory. > So, add support to relocate purgatory in kexec_file_load

[PATCH v2 08/14] powerpc/eeh: Pass eeh_dev to eeh_ops->resume_notify()

2020-07-21 Thread Oliver O'Halloran
Mechanical conversion of the eeh_ops interfaces to use eeh_dev to reference a specific device rather than pci_dn. No functional changes. Signed-off-by: Oliver O'Halloran --- v2: no changes --- arch/powerpc/include/asm/eeh.h | 2 +- arch/powerpc/kernel/eeh_driver.c | 4

Re: [PATCH 05/15] powerpc/powernv/sriov: Move SR-IOV into a seperate file

2020-07-21 Thread Oliver O'Halloran
On Tue, Jul 14, 2020 at 7:16 PM Alexey Kardashevskiy wrote: > > On 10/07/2020 15:23, Oliver O'Halloran wrote: > > + align = pci_iov_resource_size(pdev, resno); > > + > > + /* > > + * iov can be null if we have an SR-IOV device with IOV BAR that can't > > + * be placed in the m64

Re: [PATCH v2 02/10] powerpc/smp: Merge Power9 topology with Power topology

2020-07-21 Thread Gautham R Shenoy
On Tue, Jul 21, 2020 at 05:08:06PM +0530, Srikar Dronamraju wrote: > A new sched_domain_topology_level was added just for Power9. However the > same can be achieved by merging powerpc_topology with power9_topology > and makes the code more simpler especially when adding a new sched > domain. > >

Re: [PATCH v4 5/7] powerpc/iommu: Move iommu_table cleaning routine to iommu_table_clean

2020-07-21 Thread Brian King
On 7/21/20 5:13 PM, Leonardo Bras wrote: > On Tue, 2020-07-21 at 14:59 +1000, Alexey Kardashevskiy wrote: >> >> On 16/07/2020 17:16, Leonardo Bras wrote: >>> Move the part of iommu_table_free() that does struct iommu_table cleaning >>> into iommu_table_clean, so we can invoke it separately. >>>

Re: [PATCH v4 5/7] powerpc/iommu: Move iommu_table cleaning routine to iommu_table_clean

2020-07-21 Thread Alexey Kardashevskiy
On 22/07/2020 08:13, Leonardo Bras wrote: > On Tue, 2020-07-21 at 14:59 +1000, Alexey Kardashevskiy wrote: >> >> On 16/07/2020 17:16, Leonardo Bras wrote: >>> Move the part of iommu_table_free() that does struct iommu_table cleaning >>> into iommu_table_clean, so we can invoke it separately.

Re: [PATCH 5/5] powerpc sstep: Add tests for Prefixed Add Immediate

2020-07-21 Thread Jordan Niethe
On Mon, May 25, 2020 at 1:00 PM Jordan Niethe wrote: > > Use the existing support for testing compute type instructions to test > Prefixed Add Immediate (paddi). The R bit of the paddi instruction > controls whether current instruction address is used. Add test cases for > when R=1 and for R=0.

[PATCHv3 1/2] powerpc/pseries: group lmb operation and memblock's

2020-07-21 Thread Pingfan Liu
This patch prepares for the incoming patch which swaps the order of KOBJ_ uevent and dt's updating. It has no functional effect, just groups lmb operation and memblock's in order to insert dt updating operation easily, and makes it easier to review. Signed-off-by: Pingfan Liu Cc: Michael

[PATCH v2 02/14] powerpc/eeh: Remove eeh_dev.c

2020-07-21 Thread Oliver O'Halloran
The only thing in this file is eeh_dev_init() which is allocates and initialises an eeh_dev based on a pci_dn. This is only ever called from pci_dn.c so move it into there and remove the file. Signed-off-by: Oliver O'Halloran --- v2: no change --- arch/powerpc/include/asm/eeh.h | 6

[PATCH v2 01/14] powerpc/eeh: Remove eeh_dev_phb_init_dynamic()

2020-07-21 Thread Oliver O'Halloran
This function is a one line wrapper around eeh_phb_pe_create() and despite the name it doesn't create any eeh_dev structures. Replace it with direct calls to eeh_phb_pe_create() since that does what it says on the tin and removes a layer of indirection. Signed-off-by: Oliver O'Halloran --- v2:

[PATCH v2 14/14] powerpc/eeh: Move PE tree setup into the platform

2020-07-21 Thread Oliver O'Halloran
The EEH core has a concept of a "PE tree" to support PowerNV. The PE tree follows the PCI bus structures because a reset asserted on an upstream bridge will be propagated to the downstream bridges. On pseries there's a 1-1 correspondence between what the guest sees are a PHB and a PE so the "tree"

[PATCH] selftests/powerpc: Add test of memcmp at end of page

2020-07-21 Thread Michael Ellerman
Update our memcmp selftest, to test the case where we're comparing up to the end of a page and the subsequent page is not mapped. We have to make sure we don't read off the end of the page and cause a fault. We had a bug there in the past, fixed in commit d9470757398a ("powerpc/64: Fix memcmp

[PATCHv3 2/2] powerpc/pseries: update device tree before ejecting hotplug uevents

2020-07-21 Thread Pingfan Liu
A bug is observed on pseries by taking the following steps on rhel: -1. drmgr -c mem -r -q 5 -2. echo c > /proc/sysrq-trigger And then, the failure looks like: kdump: saving to /sysroot//var/crash/127.0.0.1-2020-01-16-02:06:14/ kdump: saving vmcore-dmesg.txt kdump: saving vmcore-dmesg.txt

Re: [v3 04/15] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-07-21 Thread Jordan Niethe
On Sat, Jul 18, 2020 at 1:02 AM Athira Rajeev wrote: > > From: Madhavan Srinivasan > > PowerISA v3.1 includes new performance monitoring unit(PMU) > special purpose registers (SPRs). They are > > Monitor Mode Control Register 3 (MMCR3) > Sampled Instruction Event Register 2 (SIER2) > Sampled

[PATCH v2 12/14] powerpc/eeh: Rename eeh_{add_to|remove_from}_parent_pe()

2020-07-21 Thread Oliver O'Halloran
The naming of eeh_{add_to|remove_from}_parent_pe() doesn't really reflect what they actually do. If the PE referred to be edev->pe_config_addr already exists under that PHB then the edev is added to that PE. However, if the PE doesn't exist the a new one is created for the edev. The bulk of the

[PATCH v2 11/14] powerpc/eeh: Remove class code field from edev

2020-07-21 Thread Oliver O'Halloran
The edev->class_code field is never referenced anywhere except for the platform specific probe functions. The same information is available in the pci_dev for PowerNV and in the pci_dn on pseries so we can remove the field. Signed-off-by: Oliver O'Halloran --- v2: no changes ---

Re: [PATCH 15/15] powerpc/powernv/sriov: Make single PE mode a per-BAR setting

2020-07-21 Thread Oliver O'Halloran
On Wed, Jul 15, 2020 at 6:00 PM Alexey Kardashevskiy wrote: > > >>>* > >>> - * Generally, one M64 BAR maps one IOV BAR. To avoid > >>> conflict > >>> - * with other devices, IOV BAR size is expanded to be > >>> - * (total_pe * VF_BAR_size).

[PATCH v2 03/14] powerpc/eeh: Move vf_index out of pci_dn and into eeh_dev

2020-07-21 Thread Oliver O'Halloran
Drivers that do not support the PCI error handling callbacks are handled by tearing down the device and re-probing them. If the device being removed is a virtual function then we need to know the VF index so it can be removed using the pci_iov_{add|remove}_virtfn() API. Currently this is handled

[PATCH v2 04/14] powerpc/pseries: Stop using pdn->pe_number

2020-07-21 Thread Oliver O'Halloran
The pci_dn->pe_number field is mainly used to track the IODA PE number of a device on PowerNV. At some point it grew a user in the pseries SR-IOV support which muddies the waters a bit, so remove it. Signed-off-by: Oliver O'Halloran Reviewed-by: Alexey Kardashevskiy --- v2: no change ---

[PATCH v2 13/14] powerpc/eeh: Drop pdn use in eeh_pe_tree_insert()

2020-07-21 Thread Oliver O'Halloran
This is mostly just to make the subsequent diffs less noisy. No functional changes. One thing that needs calling out is the removal of the "config_addr" variable and replacing it with edev->bdfn. The contents of edev->bdfn are the same, however it's worth pointing out that what RTAS calls a

Re: [PATCH v2 04/10] powerpc/smp: Enable small core scheduling sooner

2020-07-21 Thread Gautham R Shenoy
Hello Srikar, On Tue, Jul 21, 2020 at 05:08:08PM +0530, Srikar Dronamraju wrote: > Enable small core scheduling as soon as we detect that we are in a > system that supports thread group. Doing so would avoid a redundant > check. The patch looks good to me. However, I think the commit message

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Palmer Dabbelt
On Tue, 21 Jul 2020 16:11:02 PDT (-0700), b...@kernel.crashing.org wrote: On Tue, 2020-07-21 at 14:36 -0400, Alex Ghiti wrote: > > I guess I don't understand why this is necessary at all. > > Specifically: why > > can't we just relocate the kernel within the linear map? That would > > let the

Re: [PATCH v2 1/3] powerpc: inline doorbell sending functions

2020-07-21 Thread Michael Ellerman
Nicholas Piggin writes: > These are only called in one place for a given platform, so inline them > for performance. > > Signed-off-by: Nicholas Piggin > --- > arch/powerpc/include/asm/dbell.h | 63 ++-- > arch/powerpc/kernel/dbell.c | 55

[PATCH v2 06/14] powerpc/eeh: Remove VF config space restoration

2020-07-21 Thread Oliver O'Halloran
There's a bunch of strange things about this code. First up is that none of the fields being written to are functional for a VF. The SR-IOV specification lists then as "Reserved, but OS should preserve" so writing new values to them doesn't do anything and is clearly wrong from a correctness

Re: [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR

2020-07-21 Thread Michael Ellerman
Athira Rajeev writes: >> On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote: >> On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote: >>> Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers >>> in a flat array in order: mmcr0, mmcr1, mmcra, mmcr2, mmcrs >>> Split this to

Re: [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR

2020-07-21 Thread Michael Ellerman
Paul Mackerras writes: > On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote: >> Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers >> in a flat array in order: mmcr0, mmcr1, mmcra, mmcr2, mmcrs >> Split this to give mmcra and mmcrs its own entries in vcpu and >> use a

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Michael Ellerman
Benjamin Herrenschmidt writes: > On Tue, 2020-07-21 at 16:48 -0700, Palmer Dabbelt wrote: >> > Why ? Branch distance limits ? You can't use trampolines ? >> >> Nothing fundamental, it's just that we don't have a large code model in the C >> compiler. As a result all the global symbols are

Re: [PATCH v4 2/3] powerpc/powernv/idle: Rename pnv_first_spr_loss_level variable

2020-07-21 Thread Gautham R Shenoy
On Tue, Jul 21, 2020 at 09:07:07PM +0530, Pratik Rajesh Sampat wrote: > Replace the variable name from using "pnv_first_spr_loss_level" to > "deep_spr_loss_state". > > pnv_first_spr_loss_level is supposed to be the earliest state that > has OPAL_PM_LOSE_FULL_CONTEXT set, in other places the

Re: [RFC PATCH] powerpc/pseries/svm: capture instruction faulting on MMIO access, in sprg0 register

2020-07-21 Thread Michael Ellerman
Ram Pai writes: > An instruction accessing a mmio address, generates a HDSI fault. This fault > is > appropriately handled by the Hypervisor. However in the case of secureVMs, > the > fault is delivered to the ultravisor. > > Unfortunately the Ultravisor has no correct-way to fetch the

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Benjamin Herrenschmidt
On Tue, 2020-07-21 at 16:48 -0700, Palmer Dabbelt wrote: > > Why ? Branch distance limits ? You can't use trampolines ? > > Nothing fundamental, it's just that we don't have a large code model in the C > compiler. As a result all the global symbols are resolved as 32-bit > PC-relative accesses.

[PATCH v2 05/14] powerpc/eeh: Kill off eeh_ops->get_pe_addr()

2020-07-21 Thread Oliver O'Halloran
This is used in precisely one place which is in pseries specific platform code. There's no need to have the callback in eeh_ops since the platform chooses the EEH PE addresses anyway. The PowerNV implementation has always been a stub too so remove it. Signed-off-by: Oliver O'Halloran

Re: [PATCHv3 2/2] powerpc/pseries: update device tree before ejecting hotplug uevents

2020-07-21 Thread Michael Ellerman
Pingfan Liu writes: > A bug is observed on pseries by taking the following steps on rhel: ^ RHEL I assume it happens on mainline too? > -1. drmgr -c mem -r -q 5 > -2.

Re: [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR

2020-07-21 Thread Paul Mackerras
On Wed, Jul 22, 2020 at 07:39:26AM +0530, Athira Rajeev wrote: > > > > On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote: > > > > On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote: > >> Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers > >> in a flat array in

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Palmer Dabbelt
On Tue, 21 Jul 2020 21:50:42 PDT (-0700), m...@ellerman.id.au wrote: Benjamin Herrenschmidt writes: On Tue, 2020-07-21 at 16:48 -0700, Palmer Dabbelt wrote: > Why ? Branch distance limits ? You can't use trampolines ? Nothing fundamental, it's just that we don't have a large code model in

Re: [PATCH 5/5] powerpc sstep: Add tests for Prefixed Add Immediate

2020-07-21 Thread Michael Ellerman
Jordan Niethe writes: > On Mon, May 25, 2020 at 1:00 PM Jordan Niethe wrote: >> >> Use the existing support for testing compute type instructions to test >> Prefixed Add Immediate (paddi). The R bit of the paddi instruction >> controls whether current instruction address is used. Add test cases

Re: [RFC PATCH] powerpc/pseries/svm: capture instruction faulting on MMIO access, in sprg0 register

2020-07-21 Thread Benjamin Herrenschmidt
On Wed, 2020-07-22 at 12:06 +1000, Michael Ellerman wrote: > Ram Pai writes: > > An instruction accessing a mmio address, generates a HDSI fault. This > > fault is > > appropriately handled by the Hypervisor. However in the case of secureVMs, > > the > > fault is delivered to the ultravisor.

[PATCH] powerpc/40x: Fix assembler warning about r0

2020-07-21 Thread Michael Ellerman
The assembler says: arch/powerpc/kernel/head_40x.S:623: Warning: invalid register expression It's objecting to the use of r0 as the RA argument. That's because when RA = 0 the literal value 0 is used, rather than the content of r0, making the use of r0 in the source potentially confusing. Fix

Re: [PATCH 2/2] powerpc/numa: Remove a redundant variable

2020-07-21 Thread Nathan Lynch
Srikar Dronamraju writes: > In of_drconf_to_nid_single() default_nid always refers to NUMA_NO_NODE. > Hence replace it with NUMA_NO_NODE. > > No functional changes. > ... > diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c > index a2c5fe0d0cad..b066d89c2975 100644 > ---

OF: Can't handle multiple dma-ranges with different offsets

2020-07-21 Thread Chris Packham
Hi, I've just fired up linux kernel v5.7 on a p2040 based system and I'm getting the following new warning OF: Can't handle multiple dma-ranges with different offsets on node(/pcie@ffe202000) OF: Can't handle multiple dma-ranges with different offsets on node(/pcie@ffe202000) The warning

[PATCH v2 09/14] powerpc/eeh: Pass eeh_dev to eeh_ops->{read|write}_config()

2020-07-21 Thread Oliver O'Halloran
Mechanical conversion of the eeh_ops interfaces to use eeh_dev to reference a specific device rather than pci_dn. No functional changes. Signed-off-by: Oliver O'Halloran --- v2: no change --- arch/powerpc/include/asm/eeh.h | 4 +- arch/powerpc/kernel/eeh.c| 22

[PATCH v2 10/14] powerpc/eeh: Remove spurious use of pci_dn in eeh_dump_dev_log

2020-07-21 Thread Oliver O'Halloran
Retrieve the domain, bus, device, and function numbers from the edev. Signed-off-by: Oliver O'Halloran --- v2: no change --- arch/powerpc/kernel/eeh.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c index

Re: [RFC PATCH] powerpc/pseries/svm: capture instruction faulting on MMIO access, in sprg0 register

2020-07-21 Thread Paul Mackerras
On Thu, Jul 16, 2020 at 01:32:13AM -0700, Ram Pai wrote: > An instruction accessing a mmio address, generates a HDSI fault. This fault > is > appropriately handled by the Hypervisor. However in the case of secureVMs, > the > fault is delivered to the ultravisor. > > Unfortunately the

Re: [PATCH v4 5/7] powerpc/iommu: Move iommu_table cleaning routine to iommu_table_clean

2020-07-21 Thread Leonardo Bras
On Tue, 2020-07-21 at 14:59 +1000, Alexey Kardashevskiy wrote: > > On 16/07/2020 17:16, Leonardo Bras wrote: > > Move the part of iommu_table_free() that does struct iommu_table cleaning > > into iommu_table_clean, so we can invoke it separately. > > > > This new function is useful for cleaning

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-21 Thread Palmer Dabbelt
On Tue, 21 Jul 2020 16:12:58 PDT (-0700), b...@kernel.crashing.org wrote: On Tue, 2020-07-21 at 12:05 -0700, Palmer Dabbelt wrote: * We waste vmalloc space on 32-bit systems, where there isn't a lot of it. * On 64-bit systems the VA space around the kernel is precious because it's the only

Re: [PATCH 1/2] powerpc/numa: Limit possible nodes to within num_possible_nodes

2020-07-21 Thread Nathan Lynch
Srikar Dronamraju writes: > MAX_NUMNODES is a theoretical maximum number of nodes thats is supported > by the kernel. Device tree properties exposes the number of possible > nodes on the current platform. The kernel would detected this and would > use it for most of its resource allocations. If

[PATCH v2 07/14] powerpc/eeh: Pass eeh_dev to eeh_ops->restore_config()

2020-07-21 Thread Oliver O'Halloran
Mechanical conversion of the eeh_ops interfaces to use eeh_dev to reference a specific device rather than pci_dn. No functional changes. Signed-off-by: Oliver O'Halloran --- v2: no changes --- arch/powerpc/include/asm/eeh.h | 2 +- arch/powerpc/kernel/eeh.c| 5

Re: [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-21 Thread Jordan Niethe
On Sat, Jul 18, 2020 at 1:13 AM Athira Rajeev wrote: > > From: Madhavan Srinivasan > > Add power10 feature function to dt_cpu_ftrs.c along > with a power10 specific init() to initialize pmu sprs, > sets the oprofile_cpu_type and cpu_features. This will > enable performance monitoring unit(PMU)

Re: [PATCH 09/20] Documentation: i2c: eliminate duplicated word

2020-07-21 Thread Wolfram Sang
On Tue, Jul 07, 2020 at 11:04:03AM -0700, Randy Dunlap wrote: > Drop doubled word "new". > > Signed-off-by: Randy Dunlap > Cc: Jonathan Corbet > Cc: linux-...@vger.kernel.org > Cc: Wolfram Sang > Cc: linux-...@vger.kernel.org Reviewed-by: Wolfram Sang signature.asc Description: PGP

Re: [v3 13/15] tools/perf: Add perf tools support for extended register capability in powerpc

2020-07-21 Thread kajoljain
On 7/17/20 8:08 PM, Athira Rajeev wrote: > From: Anju T Sudhakar > > Add extended regs to sample_reg_mask in the tool side to use > with `-I?` option. Perf tools side uses extended mask to display > the platform supported register names (with -I? option) to the user > and also send this mask

Re: [RFC PATCH] powerpc/pseries/svm: capture instruction faulting on MMIO access, in sprg0 register

2020-07-21 Thread Laurent Dufour
Le 20/07/2020 à 22:24, Segher Boessenkool a écrit : On Mon, Jul 20, 2020 at 03:10:41PM -0500, Segher Boessenkool wrote: On Mon, Jul 20, 2020 at 11:39:56AM +0200, Laurent Dufour wrote: Le 16/07/2020 à 10:32, Ram Pai a écrit : + if (is_secure_guest()) {

Re: [PATCH v4 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-21 Thread Ravi Bangoria
On 7/17/20 11:14 AM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:10 PM Ravi Bangoria wrote: Add new device-tree feature for 2nd DAWR. If this feature is present, 2nd DAWR is supported, otherwise not. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 7 +--

Re: [v3 12/15] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-07-21 Thread kajoljain
On 7/17/20 8:08 PM, Athira Rajeev wrote: > From: Anju T Sudhakar > > Add support for perf extended register capability in powerpc. > The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the > PMU which support extended registers. The generic code define the mask > of extended

Re: [v3 15/15] tools/perf: Add perf tools support for extended regs in power10

2020-07-21 Thread kajoljain
On 7/17/20 8:08 PM, Athira Rajeev wrote: > Added support for supported regs which are new in power10 > ( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side > to use with `-I?` option. Also added PVR check to send extended > mask for power10 at kernel while capturing extended regs in >

Re: [v3 14/15] powerpc/perf: Add extended regs support for power10 platform

2020-07-21 Thread kajoljain
On 7/17/20 8:08 PM, Athira Rajeev wrote: > Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10 > and expose MMCR3, SIER2, SIER3 registers as part of extended regs. > Also introduce `PERF_REG_PMU_MASK_31` to define extended mask > value at runtime for power10 > > Signed-off-by:

Re: [PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-21 Thread Ravi Bangoria
@@ -46,7 +47,7 @@ struct arch_hw_breakpoint { static inline int nr_wp_slots(void) { - return HBP_NUM_MAX; + return cpu_has_feature(CPU_FTR_DAWR1) ? HBP_NUM_TWO : HBP_NUM_ONE; So it'd be something like: + return cpu_has_feature(CPU_FTR_DAWR1) ? HBP_NUM_MAX : 1; But

Re: [PATCH v3 0/6] powerpc: queued spinlocks and rwlocks

2020-07-21 Thread Nicholas Piggin
Excerpts from Peter Zijlstra's message of July 8, 2020 6:41 pm: > On Tue, Jul 07, 2020 at 03:57:06PM +1000, Nicholas Piggin wrote: >> Yes, powerpc could certainly get more performance out of the slow >> paths, and then there are a few parameters to tune. > Sorry for the delay, got bogged down

[PATCH v2 06/10] powerpc/smp: Generalize 2nd sched domain

2020-07-21 Thread Srikar Dronamraju
Currently "CACHE" domain happens to be the 2nd sched domain as per powerpc_topology. This domain will collapse if cpumask of l2-cache is same as SMT domain. However we could generalize this domain such that it could mean either be a "CACHE" domain or a "BIGCORE" domain. While setting up the

[PATCH v2 07/10] Powerpc/numa: Detect support for coregroup

2020-07-21 Thread Srikar Dronamraju
Add support for grouping cores based on the device-tree classification. - The last domain in the associativity domains always refers to the core. - If primary reference domain happens to be the penultimate domain in the associativity domains device-tree property, then there are no coregroups.

Re: [PATCH v3 0/4] powerpc/mm/radix: Memory unplug fixes

2020-07-21 Thread Michael Ellerman
Bharata B Rao writes: > On Tue, Jul 21, 2020 at 11:45:20AM +1000, Michael Ellerman wrote: >> Nathan Lynch writes: >> > "Aneesh Kumar K.V" writes: >> >> This is the next version of the fixes for memory unplug on radix. >> >> The issues and the fix are described in the actual patches. >> > >> > I

[PATCH v2 00/10] Coregroup support on Powerpc

2020-07-21 Thread Srikar Dronamraju
Changelog v1 -> v2: v1: https://lore.kernel.org/linuxppc-dev/20200714043624.5648-1-sri...@linux.vnet.ibm.com/t/#u powerpc/smp: Merge Power9 topology with Power topology Replaced a reference to cpu_smt_mask with per_cpu(cpu_sibling_map, cpu) since cpu_smt_mask is only defined

[PATCH v2 05/10] powerpc/smp: Dont assume l2-cache to be superset of sibling

2020-07-21 Thread Srikar Dronamraju
Current code assumes that cpumask of cpus sharing a l2-cache mask will always be a superset of cpu_sibling_mask. Lets stop that assumption. cpu_l2_cache_mask is a superset of cpu_sibling_mask if and only if shared_caches is set. Cc: linuxppc-dev Cc: LKML Cc: Michael Ellerman Cc: Ingo Molnar

[PATCH v2 04/10] powerpc/smp: Enable small core scheduling sooner

2020-07-21 Thread Srikar Dronamraju
Enable small core scheduling as soon as we detect that we are in a system that supports thread group. Doing so would avoid a redundant check. Cc: linuxppc-dev Cc: LKML Cc: Michael Ellerman Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Valentin Schneider Cc: Nick Piggin Cc: Oliver OHalloran Cc:

[PATCH v3 1/2] cpuidle: Trace IPI based and timer based wakeup latency from idle states

2020-07-21 Thread Pratik Rajesh Sampat
Fire directed smp_call_function_single IPIs from a specified source CPU to the specified target CPU to reduce the noise we have to wade through in the trace log. The module is based on the idea written by Srivatsa Bhat and maintained by Vaidyanathan Srinivasan internally. Queue HR timer and

[PATCH v3 0/2] Selftest for cpuidle latency measurement

2020-07-21 Thread Pratik Rajesh Sampat
v2: https://lkml.org/lkml/2020/7/17/369 Changelog v2-->v3 Based on comments from Gautham R. Shenoy adding the following in the selftest, 1. Grepping modules to determine if already loaded 2. Wrapper to enable/disable states 3. Preventing any operation/test on offlined CPUs --- The patch series

Re: [PATCH v3 0/6] powerpc: queued spinlocks and rwlocks

2020-07-21 Thread Nicholas Piggin
Excerpts from Peter Zijlstra's message of July 9, 2020 6:31 pm: > On Wed, Jul 08, 2020 at 07:54:34PM -0400, Waiman Long wrote: >> On 7/8/20 4:41 AM, Peter Zijlstra wrote: >> > On Tue, Jul 07, 2020 at 03:57:06PM +1000, Nicholas Piggin wrote: >> > > Yes, powerpc could certainly get more performance

Re: [PATCH v4 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-21 Thread Michael Ellerman
Ravi Bangoria writes: > On 7/17/20 11:14 AM, Jordan Niethe wrote: >> On Fri, Jul 17, 2020 at 2:10 PM Ravi Bangoria >> wrote: >>> >>> Add new device-tree feature for 2nd DAWR. If this feature is present, >>> 2nd DAWR is supported, otherwise not. >>> >>> Signed-off-by: Ravi Bangoria >>> --- >>>

Re: [PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-21 Thread Michael Ellerman
Ravi Bangoria writes: > On 7/20/20 9:12 AM, Jordan Niethe wrote: >> On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria >> wrote: >>> >>> So far Book3S Powerpc supported only one watchpoint. Power10 is >>> introducing 2nd DAWR. Enable 2nd DAWR support for Power10. >>> Availability of 2nd DAWR will

[PATCH v2 01/10] powerpc/smp: Cache node for reuse

2020-07-21 Thread Srikar Dronamraju
While cpu_to_node is inline function with access to per_cpu variable. However when using repeatedly, it may be cleaner to cache it in a local variable. Also fix a build error in a some weird config. "error: _numa_cpu_lookup_table_ undeclared" No functional change Cc: linuxppc-dev Cc: LKML Cc:

[PATCH v2 02/10] powerpc/smp: Merge Power9 topology with Power topology

2020-07-21 Thread Srikar Dronamraju
A new sched_domain_topology_level was added just for Power9. However the same can be achieved by merging powerpc_topology with power9_topology and makes the code more simpler especially when adding a new sched domain. Cc: linuxppc-dev Cc: LKML Cc: Michael Ellerman Cc: Ingo Molnar Cc: Peter

[PATCH v2 08/10] powerpc/smp: Allocate cpumask only after searching thread group

2020-07-21 Thread Srikar Dronamraju
If allocated earlier and the search fails, then cpumask need to be freed. However cpu_l1_cache_map can be allocated after we search thread group. Cc: linuxppc-dev Cc: LKML Cc: Michael Ellerman Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Valentin Schneider Cc: Nick Piggin Cc: Oliver OHalloran

[PATCH v2 09/10] Powerpc/smp: Create coregroup domain

2020-07-21 Thread Srikar Dronamraju
Add percpu coregroup maps and masks to create coregroup domain. If a coregroup doesn't exist, the coregroup domain will be degenerated in favour of SMT/CACHE domain. Cc: linuxppc-dev Cc: LKML Cc: Michael Ellerman Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Valentin Schneider Cc: Nick Piggin Cc:

[PATCH v2 10/10] powerpc/smp: Implement cpu_to_coregroup_id

2020-07-21 Thread Srikar Dronamraju
Lookup the coregroup id from the associativity array. If unable to detect the coregroup id, fallback on the core id. This way, ensure sched_domain degenerates and an extra sched domain is not created. Ideally this function should have been implemented in arch/powerpc/kernel/smp.c. However if its

[PATCH v2 03/10] powerpc/smp: Move powerpc_topology above

2020-07-21 Thread Srikar Dronamraju
Just moving the powerpc_topology description above. This will help in using functions in this file and avoid declarations. No other functional changes Cc: linuxppc-dev Cc: LKML Cc: Michael Ellerman Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Valentin Schneider Cc: Nick Piggin Cc: Oliver

Re: [PATCH v2 2/2] selftest/cpuidle: Add support for cpuidle latency measurement

2020-07-21 Thread Pratik Sampat
Hi Gautham, Thanks for the review. On 20/07/20 11:22 am, Gautham R Shenoy wrote: Hi Pratik, On Fri, Jul 17, 2020 at 02:48:01PM +0530, Pratik Rajesh Sampat wrote: This patch adds support to trace IPI based and timer based wakeup latency from idle states Latches onto the test-cpuidle_latency

[PATCH v3 2/2] selftest/cpuidle: Add support for cpuidle latency measurement

2020-07-21 Thread Pratik Rajesh Sampat
This patch adds support to trace IPI based and timer based wakeup latency from idle states Latches onto the test-cpuidle_latency kernel module using the debugfs interface to send IPIs or schedule a timer based event, which in-turn populates the debugfs with the latency measurements. Currently

[PATCH v2 0/2] Rework secure memslot dropping

2020-07-21 Thread Laurent Dufour
When doing memory hotplug on a secure VM, the secure pages are not well cleaned from the secure device when dropping the memslot. This silent error, is then preventing the SVM to reboot properly after the following sequence of commands are run in the Qemu monitor: device_add

[PATCH trivial] ppc64/mm: remove comment that is no longer valid

2020-07-21 Thread Santosh Sivaraj
hash_low_64.S was removed in [1] and since flush_hash_page is not called from any assembly routine. [1]: commit a43c0eb8364c0 ("powerpc/mm: Convert 4k insert from asm to C") Signed-off-by: Santosh Sivaraj --- arch/powerpc/mm/book3s64/hash_utils.c | 4 1 file changed, 4 deletions(-) diff

[PATCH v2 1/2] KVM: PPC: Book3S HV: move kvmppc_svm_page_out up

2020-07-21 Thread Laurent Dufour
kvmppc_svm_page_out() will need to be called by kvmppc_uvmem_drop_pages() so move it upper in this file. Furthermore it will be interesting to call this function when already holding the kvm->arch.uvmem_lock, so prefix the original function with __ and remove the locking in it, and introduce a

Re: [PATCH v3] powerpc/pseries: Avoid using addr_to_pfn in realmode

2020-07-21 Thread Nicholas Piggin
Excerpts from Ganesh Goudar's message of July 20, 2020 6:03 pm: > When an UE or memory error exception is encountered the MCE handler > tries to find the pfn using addr_to_pfn() which takes effective > address as an argument, later pfn is used to poison the page where > memory error occurred,

Re: [PATCH v3 1/3] powerpc/powernv/idle: Replace CPU features checks with PVR checks

2020-07-21 Thread Pratik Sampat
On 20/07/20 5:30 am, Nicholas Piggin wrote: Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am: As the idle framework's architecture is incomplete, hence instead of checking for just the processor type advertised in the device tree CPU features; check for the Processor

Re: [RFC PATCH 4/7] x86: use exit_lazy_tlb rather than membarrier_mm_sync_core_before_usermode

2020-07-21 Thread Nicholas Piggin
Excerpts from Mathieu Desnoyers's message of July 21, 2020 2:46 am: > - On Jul 19, 2020, at 11:03 PM, Nicholas Piggin npig...@gmail.com wrote: > >> Excerpts from Mathieu Desnoyers's message of July 17, 2020 11:42 pm: >>> - On Jul 16, 2020, at 7:26 PM, Nicholas Piggin npig...@gmail.com

Re: [PATCH v3 2/3] powerpc/powernv/idle: Rename pnv_first_spr_loss_level variable

2020-07-21 Thread Pratik Sampat
On 20/07/20 5:27 am, Nicholas Piggin wrote: Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am: Replace the variable name from using "pnv_first_spr_loss_level" to "pnv_first_fullstate_loss_level". As pnv_first_spr_loss_level is supposed to be the earliest state that has

[PATCH v2 2/2] KVM: PPC: Book3S HV: rework secure mem slot dropping

2020-07-21 Thread Laurent Dufour
When a secure memslot is dropped, all the pages backed in the secure device (aka really backed by secure memory by the Ultravisor) should be paged out to a normal page. Previously, this was achieved by triggering the page fault mechanism which is calling kvmppc_svm_page_out() on each pages. This

Re: [PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-21 Thread Ravi Bangoria
On 7/21/20 5:06 PM, Michael Ellerman wrote: Ravi Bangoria writes: On 7/20/20 9:12 AM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria wrote: So far Book3S Powerpc supported only one watchpoint. Power10 is introducing 2nd DAWR. Enable 2nd DAWR support for Power10.

Re: [PATCH v4 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-21 Thread Ravi Bangoria
On 7/21/20 4:59 PM, Michael Ellerman wrote: Ravi Bangoria writes: On 7/17/20 11:14 AM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:10 PM Ravi Bangoria wrote: Add new device-tree feature for 2nd DAWR. If this feature is present, 2nd DAWR is supported, otherwise not. Signed-off-by:

Re: [PATCH v3 2/3] powerpc/powernv/idle: Rename pnv_first_spr_loss_level variable

2020-07-21 Thread Nicholas Piggin
Excerpts from Pratik Sampat's message of July 21, 2020 8:29 pm: > > > On 20/07/20 5:27 am, Nicholas Piggin wrote: >> Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am: >>> Replace the variable name from using "pnv_first_spr_loss_level" to >>> "pnv_first_fullstate_loss_level".

Re: [RFC PATCH 4/7] x86: use exit_lazy_tlb rather than membarrier_mm_sync_core_before_usermode

2020-07-21 Thread Mathieu Desnoyers
- On Jul 21, 2020, at 6:04 AM, Nicholas Piggin npig...@gmail.com wrote: > Excerpts from Mathieu Desnoyers's message of July 21, 2020 2:46 am: [...] > > Yeah you're probably right in this case I think. Quite likely most kernel > tasks that asynchronously write to user memory would at least

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