Perf all metrics test fails as below when perf_event access
is restricted.
./perf test -v "perf all metrics test"
Metric 'Memory_RD_BW_Chip' not printed in:
Error:
Access to performance monitoring and observability operations is limited.
Enforced MAC policy settings (SELinux)
Perf all metricgroups test fails as below when perf_event access
is restricted.
./perf test -v "perf all metricgroups test"
Testing Memory_BW
Error:
Access to performance monitoring and observability operations is limited.
Enforced MAC policy settings (SELinux) can limit
On Mon, 12 Jun 2023, Vishal Moola (Oracle) wrote:
> Currently, page table information is stored within struct page. As part
> of simplifying struct page, create struct ptdesc for page table
> information.
>
> Signed-off-by: Vishal Moola (Oracle)
Vishal, as I think you have already guessed,
ppc_save_regs() skips one stack frame while saving the CPU register states.
Instead of saving current R1, it pulls the previous stack frame pointer.
When vmcores caused by direct panic call (such as `echo c >
/proc/sysrq-trigger`), are debugged with gdb, gdb fails to show the
backtrace correctly.
There's code in prom_instantiate_sml() to do a "SML handover" (Stored
Measurement Log) from OF to Linux, before Linux shuts down Open
Firmware.
This involves creating a buffer to hold the SML, and creating two device
tree properties to record its base address and size. The kernel then
later reads
[CCing the regression list, as it should be in the loop for regressions:
https://docs.kernel.org/admin-guide/reporting-regressions.html]
[TLDR: I'm adding this report to the list of tracked Linux kernel
regressions; the text you find below is based on a few templates
paragraphs you might have
On Thu Jun 15, 2023 at 7:10 PM AEST, Aditya Gupta wrote:
> ppc_save_regs() skips one stack frame while saving the CPU register states.
> Instead of saving current R1, it pulls the previous stack frame pointer.
>
> When vmcores caused by direct panic call (such as `echo c >
> /proc/sysrq-trigger`),
The TPM code in prom_init.c creates a small buffer of memory to store
the TPM's SML (Stored Measurement Log). It's communicated to Linux via
the linux,sml-base/size device tree properties of the TPM node.
When kexec'ing that buffer can be overwritten, or when kdump'ing it may
not be mapped by the
The minimum level of gcc supported for building the kernel is v5.1.
v5.x releases of gcc emitted a three instruction sequence for
-mprofile-kernel:
mflrr0
std r0, 16(r1)
bl _mcount
It is only with the v6.x releases that gcc started emitting the two
instruction
On Thu, 15 Jun 2023 at 03:02, Nicholas Piggin wrote:
>
> On Wed Jun 14, 2023 at 11:09 AM AEST, Joel Stanley wrote:
> > On Thu, 8 Jun 2023 at 07:58, Nicholas Piggin wrote:
> > >
> > > Posting again, a couple of patches were merged and accounted for review
> > > comments from last time.
> >
> > I
On Mon, 15 May 2023 11:10:49 -0400, Frank Li wrote:
> Layerscape has PME interrupt, which can be used as linkup notifier.
> Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
> when linkup detected.
>
>
Applied to controller/endpoint, thanks!
[1/1] PCI: layerscape: Add
On Mon, May 15, 2023 at 11:10:49AM -0400, Frank Li wrote:
> Layerscape has PME interrupt, which can be used as linkup notifier.
> Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
> when linkup detected.
>
> Acked-by: Manivannan Sadhasivam
> Signed-off-by: Xiaowei Bao
>
Recognise and pass the appropriate signal to the user program when a
hashchk instruction triggers. This is independent of allowing
configuration of DEXCR[NPHIE], as a hypervisor can enforce this aspect
regardless of the kernel.
The signal mirrors how ARM reports their similar check failure. For
built successfully.
More configs may be tested in the coming days.
tested configs:
alphaallyesconfig gcc
alphabuildonly-randconfig-r004-20230615 gcc
alpha defconfig gcc
alpharandconfig-r002-20230615 gcc
Test the kernel DEXCR[NPHIE] interface and hashchk exception handling.
Introduces with it a DEXCR utils library for common DEXCR operations.
Volatile is used to prevent the compiler optimising away the signal
tests.
Signed-off-by: Benjamin Gray
---
v1: * Clean up dexcr makefile
*
Adds _MSG assertion variants to provide more context behind why a
failure occurred. Also include unistd.h for _exit() and stdio.h for
fprintf(), and move ARRAY_SIZE macro to utils.h.
The _MSG variants and ARRAY_SIZE will be used by the following
DEXCR selftests.
Signed-off-by: Benjamin Gray
The HASHKEYR register contains a secret per-process key to enable unique
hashes per process. In general it should not be exposed to userspace
at all and a regular process has no need to know its key.
However, checkpoint restore in userspace (CRIU) functionality requires
that a process be able to
Describe the DEXCR and document how to configure it.
Signed-off-by: Benjamin Gray
---
v3: * Revise (H)DEXCR width to 64 bits
* Revise configuration section
v2: * Document coredump & ptrace support
v1: * Remove the dynamic control docs, describe the static config
To keep balance in future, __update_tlb() remember to pte_unmap() after
pte_offset_map(). This is an odd case, since the caller has already done
pte_offset_map_lock(), then mips forgets the address and recalculates it;
but my two naive attempts to clean that up did more harm than good.
The DEXCR register is of interest when ptracing processes. Currently it
is static, but eventually will be dynamically controllable by a process.
If a process can control its own, then it is useful for it to be
ptrace-able to (e.g., for checkpoint-restore functionality).
It is also relevant to
The ISA 3.1B hashst and hashchk instructions use a per-cpu SPR HASHKEYR
to hold a key used in the hash calculation. This key should be different
for each process to make it harder for a malicious process to recreate
valid hash values for a victim process.
Add support for storing a per-thread hash
Add a utility 'lsdexcr' to print the current DEXCR status. Useful for
quickly checking the status such as when debugging test failures or
verifying the new default DEXCR does what you want (for userspace at
least). Example output:
# ./lsdexcr
uDEXCR: 0400 (NPHIE)
HDEXCR:
Le 15/06/2023 à 18:34, Randy Dunlap a écrit :
>
>
> On 6/15/23 09:13, Randy Dunlap wrote:
>>
>>
>> On 6/15/23 09:05, Timothy Pearson wrote:
>>>
>>>
>>> - Original Message -
From: "Randy Dunlap"
To: "Timothy Pearson" , "Michael Ellerman"
Cc: "Stephen Rothwell" ,
v3: * Expose (H)DEXCR in ptrace as 64 bits
* Remove build config for DEXCR, always enable NPHIE
* Fix up documentation to reflect this
* Some commit message fixes
Previous versions:
v2: https://lore.kernel.org/all/20230330055040.434133-1-bg...@linux.ibm.com/
v1:
The functions here use struct task_struct fields, so need to import
the full definition from . The header
that defines current only forward declares struct task_struct.
Failing to include this header leads to a compilation
error when a translation unit does not also include
indirectly.
With ppc64 -mprofile-kernel and ppc32 -pg, profiling instructions to
call into ftrace are emitted right at function entry. The instruction
sequence used is minimal to reduce overhead. Crucially, a stackframe is
not created for the function being traced. This breaks stack unwinding
since the
From: Michael Ellerman
A subsequent patch will enable partial SMT states, ie. when not all SMT
threads are brought online.
To support that, add an arch helper which checks whether a given CPU is
allowed to be brought online depending on how many SMT threads are
currently enabled.
Call the
I'm taking over the series Michael sent previously [1] which is smartly
reviewing the initial series I sent [2]. This series is addressing the
comments sent by Thomas and me on the Michael's one.
Here is a short introduction to the issue this series is addressing:
When a new CPU is added, the
From: Michael Ellerman
Some architectures (ppc64) allows partial SMT states at boot time, ie. when
not all SMT threads are brought online.
To support that the SMT code needs to know the maximum number of SMT
threads, and also the currently configured number.
The architecture code knows the max
Hi,
Static analysis with cppcheck has found an issue in the following commit:
commit 047e6575aec71d75b765c22111820c4776cd1c43
Author: Aneesh Kumar K.V
Date: Tue Sep 24 09:22:53 2019 +0530
powerpc/mm: Fixup tlbie vs mtpidr/mtlpidr ordering issue on POWER9
The issue in
From: Michael Ellerman
Integrate with the generic SMT support, so that when a CPU is DLPAR
onlined it is brought up with the correct SMT mode.
Signed-off-by: Michael Ellerman
---
arch/powerpc/platforms/pseries/hotplug-cpu.c | 8
1 file changed, 8 insertions(+)
diff --git
From: Michael Ellerman
A subsequent patch would like to use the cpuhp_smt_control enum as part
of the interface between generic and arch code.
Currently that leads to circular header dependencies. So split the enum
and related declarations into a separate header.
Signed-off-by: Michael
- Original Message -
> From: "Randy Dunlap"
> To: "Timothy Pearson" , "Michael Ellerman"
>
> Cc: "Stephen Rothwell" , "Linux Next Mailing List"
> , "linux-kernel"
> , "linuxppc-dev"
> , "Alexey Kardashevskiy"
> Sent: Thursday, June 15, 2023 11:00:08 AM
> Subject: Re: linux-next:
From: Michael Ellerman
A subsequent patch will enable partial SMT states, ie. when not all SMT
threads are brought online.
To support that, add an arch helper to check how many SMT threads are
supported.
To retain existing behaviour, the x86 implementation only allows a
single thread or all
From: Michael Ellerman
Add support for HOTPLUG_SMT, which enables the generic sysfs SMT support
files in /sys/devices/system/cpu/smt, as well as the "nosmt" boot
parameter.
Implement the recently added hooks to allow partial SMT states, allow
any number of threads per core.
Tie the config
On Wed, Jun 14, 2023 at 10:43:30PM -0700, Hugh Dickins wrote:
> On Wed, 14 Jun 2023, Hugh Dickins wrote:
> > On Wed, 14 Jun 2023, Nathan Chancellor wrote:
> > >
> > > I just bisected a crash while powering down a MIPS machine in QEMU to
> > > this change as commit 8044511d3893 ("mips:
On 6/15/23 09:05, Timothy Pearson wrote:
>
>
> - Original Message -
>> From: "Randy Dunlap"
>> To: "Timothy Pearson" , "Michael Ellerman"
>>
>> Cc: "Stephen Rothwell" , "Linux Next Mailing List"
>> , "linux-kernel"
>> , "linuxppc-dev"
>> , "Alexey Kardashevskiy"
>> Sent:
From: Michael Ellerman
Add support to the /sys/devices/system/cpu/smt/control interface for
enabling a specified number of SMT threads per core, including partial
SMT states where not all threads are brought online.
The current interface accepts "on" and "off", to enable either 1 or all
SMT
From: Michael Ellerman
Move the simple exit cases, ie. which don't depend on the value written,
earlier in the function. That makes it clearer that regardless of the
input those states can not be transitioned out of.
That does have a user-visible effect, in that the error returned will
now
From: Michael Ellerman
As part of the generic HOTPLUG_SMT code, there is support for disabling
secondary SMT threads at boot time, by passing "nosmt" on the kernel
command line.
The way that is implemented is the secondary threads are brought partly
online, and then taken back offline again.
Since the maximum number of threads is now passed to
cpu_smt_set_num_threads(), checking that value is enough to know if SMT is
supported.
Cc: Michael Ellerman
Suggested-by: Thomas Gleixner
Signed-off-by: Laurent Dufour
---
arch/x86/include/asm/topology.h | 2 --
arch/x86/kernel/smpboot.c
Hi Timothy,
On 6/3/23 20:57, Timothy Pearson wrote:
>
>
> - Original Message -
>> From: "Michael Ellerman"
>> To: "Randy Dunlap" , "Stephen Rothwell"
>> , "Linux Next Mailing List"
>>
>> Cc: "linux-kernel" , "linuxppc-dev"
>> , "Alexey
>> Kardashevskiy" , "Timothy Pearson"
>>
>>
On Thu, 15 Jun 2023, Nathan Chancellor wrote:
> On Wed, Jun 14, 2023 at 10:43:30PM -0700, Hugh Dickins wrote:
> >
> > I do hope that you find the first fixes the breakage; but if not, then
>
> I hate to be the bearer of bad news but the first patch did not fix the
> breakage, I see the same
On Wed, Jun 14, 2023 at 04:17:58PM -0700, Nathan Chancellor wrote:
> Hi Hugh,
>
> On Thu, Jun 08, 2023 at 12:17:24PM -0700, Hugh Dickins wrote:
> > Don't make update_mmu_cache() a wrapper around __update_tlb(): call it
> > directly, and use the ptep (or pmdp) provided by the caller, instead of
>
ptrace-decl.h uses user_regset_get2_fn (among other things) from
regset.h. While all current users of ptrace-decl.h include regset.h
before it anyway, it adds an implicit ordering dependency and breaks
source tooling that tries to inspect ptrace-decl.h by itself.
Signed-off-by: Benjamin Gray
ISA 3.1B introduces the Dynamic Execution Control Register (DEXCR). It
is a per-cpu register that allows control over various CPU behaviours
including branch hint usage, indirect branch speculation, and
hashst/hashchk support.
Add some definitions and basic support for the DEXCR in the kernel.
On 6/15/23 09:13, Randy Dunlap wrote:
>
>
> On 6/15/23 09:05, Timothy Pearson wrote:
>>
>>
>> - Original Message -
>>> From: "Randy Dunlap"
>>> To: "Timothy Pearson" , "Michael Ellerman"
>>>
>>> Cc: "Stephen Rothwell" , "Linux Next Mailing List"
>>> , "linux-kernel"
>>> ,
Add support to pass Link down notification to Endpoint function driver
so that the LINK_DOWN event can be processed by the function.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On Fri, May 26, 2023, Yu Zhao wrote:
> tdp_mmu_enabled and shadow_accessed_mask are needed to implement
> kvm_arch_has_test_clear_young().
>
> Signed-off-by: Yu Zhao
> ---
> arch/x86/include/asm/kvm_host.h | 6 ++
> arch/x86/kvm/mmu.h | 6 --
> arch/x86/kvm/mmu/spte.h
On 6/14/23 22:34, Michael Ellerman wrote:
Eric DeVolder writes:
The kexec and crash kernel options are provided in the common
kernel/Kconfig.kexec. Utilize the common options and provide
the ARCH_HAS_ and ARCH_SUPPORTS_ entries to recreate the
equivalent set of KEXEC and CRASH options.
On Fri, May 26, 2023, Yu Zhao wrote:
> diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
> index 08340219c35a..6875a819e007 100644
> --- a/arch/x86/kvm/mmu/tdp_mmu.c
> +++ b/arch/x86/kvm/mmu/tdp_mmu.c
> @@ -1232,6 +1232,40 @@ bool kvm_tdp_mmu_test_age_gfn(struct kvm *kvm, struct
On Fri, May 26, 2023, Yu Zhao wrote:
> diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
> index 0e571e973bc2..374262545f96 100644
> --- a/include/linux/kvm_host.h
> +++ b/include/linux/kvm_host.h
> @@ -258,6 +258,7 @@ int kvm_async_pf_wakeup_all(struct kvm_vcpu *vcpu);
> #ifdef
From: Xiaowei Bao
A workaround for the issue where the PCI Express Endpoint (EP) controller
loses the values of the Maximum Link Width and Supported Link Speed from
the Link Capabilities Register, which initially configured by the Reset
Configuration Word (RCW) during a link-down or hot reset
On Thu, Jun 15, 2023 at 01:34:25PM +1000, Michael Ellerman wrote:
> Eric DeVolder writes:
> > -config KEXEC_FILE
> > - bool "kexec file based system call"
> > - select KEXEC_CORE
> > - select HAVE_IMA_KEXEC if IMA
> > - select KEXEC_ELF
> > - depends on PPC64
> > - depends on CRYPTO=y
On 6/14/23 22:26, Michael Ellerman wrote:
Eric DeVolder writes:
On 6/13/23 15:21, Kees Cook wrote:
On Mon, Jun 12, 2023 at 01:27:52PM -0400, Eric DeVolder wrote:
The Kconfig is refactored to consolidate KEXEC and CRASH options from
various arch//Kconfig files into new file
On Thu, Jun 15, 2023 at 01:41:10AM +0100, Maciej W. Rozycki wrote:
> On Wed, 14 Jun 2023, Bjorn Helgaas wrote:
>
> > > This is v9 of the change to work around a PCIe link training phenomenon
> > > where a pair of devices both capable of operating at a link speed above
> > > 2.5GT/s seems
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