When processing an Advisory Non-Fatal error, ideally both correctable
error status and uncorrectable error status should be cleared. However,
there is no way to fully identify the UE associated with ANFE. Even
worse, a Fatal/Non-Fatal error may set the same UE status bit as ANFE.
Assuming an ANFE
This part was commented from commit 6d492ecc6489
("powerpc/THP: Add code to handle HPTE faults for hugepages")
in about 11 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu Chan
---
This part was commented from commit a33a7d7309d7
("[PATCH] spufs: implement mfc access for PPE-side DMA")
in about 18 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu Chan
---
arch/powerpc/platforms/cell/spufs/file.c
Le 25/01/2024 à 11:08, Kunwu Chan a écrit :
> This part was commented from commit a33a7d7309d7
> ("[PATCH] spufs: implement mfc access for PPE-side DMA")
> in about 18 years before.
>
> If there are no plans to enable this part code in the future,
> we can remove this dead code.
>
>
On PPC64, the iommu_ops.def_domain_type() is not defined and
CONFIG_IOMMU_DMA not enabled. With commit 0f6a90436a57 ("iommu: Do not
use IOMMU_DOMAIN_DMA if CONFIG_IOMMU_DMA is not enabled"), the
iommu_get_default_domain_type() return IOMMU_DOMAIN_IDENTITY. With
commit 2ad56efa80db ("powerpc/iommu:
On PowerNV and pSeries machines, the bind and unbind of vfio-pci is
broken with the below commits.
2ad56efa80db ("powerpc/iommu: Setup a default domain and remove
set_platform_dma_ops")
0f6a90436a57 ("iommu: Do not use IOMMU_DOMAIN_DMA if CONFIG_IOMMU_DMA is not
enabled")
Details of the same
The commit 2ad56efa80db ("powerpc/iommu: Setup a default domain and
remove set_platform_dma_ops") refactored the code removing the
set_platform_dma_ops(). It missed out the table group
release_ownership() call which would have got called otherwise
during the guest shutdown via
On 1/25/24 3:16 PM, Kunwu Chan wrote:
> This part was commented in about 17 years before.
> If there are no plans to enable this part code in the future,
> we can remove this dead code.
>
> Signed-off-by: Kunwu Chan
> ---
> arch/powerpc/include/asm/book3s/64/mmu-hash.h | 22 ---
Nysal reported that userspace backtraces are missing in offcputime bcc
tool. As an example:
$ sudo ./bcc/tools/offcputime.py -uU
Tracing off-CPU time (us) of user threads by user stack... Hit Ctrl-C to
end.
^C
write
-python (9107)
8
Hi!
On Thu, Jan 25, 2024 at 05:12:28PM +0530, Naveen N Rao wrote:
> diff --git a/arch/powerpc/kernel/interrupt_64.S
> b/arch/powerpc/kernel/interrupt_64.S
> index bd863702d812..5cf3758a19d3 100644
> --- a/arch/powerpc/kernel/interrupt_64.S
> +++ b/arch/powerpc/kernel/interrupt_64.S
> @@ -53,6
This part was commented in about 17 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu Chan
---
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 22 ---
1 file changed, 22 deletions(-)
diff --git
When Advisory Non-Fatal errors are raised, both correctable and
uncorrectable error statuses will be set. The current kernel code cannot
store both statuses at the same time, thus failing to handle ANFE properly.
In addition, to avoid clearing UEs that are not ANFE by accident, UE
severity and
Fetch and store the data of 3 more registers: "Link Status", "Device
Control 2", and "Advanced Error Capabilities and Control". This data is
needed for external observation to better understand ANFE.
Signed-off-by: "Wang, Qingshun"
---
drivers/acpi/apei/ghes.c | 8 +++-
According to PCIe Base Specification Revision 6.1, Sections 6.2.3.4
and 6.2.4.3, certain uncorrectable errors will signal ERR_COR instead
of ERR_NONFATAL, logged as Advisory Non-Fatal Error, and set bits in
both Correctable Error Status register and Uncorrectable Error Status
register. Currently,
Add following fields in aer_event to better understand Advisory
Non-Fatal and other errors for external observation:
- cor_status (Correctable Error Status)
- cor_mask(Correctable Error Mask)
- uncor_status(Uncorrectable Error Status)
- uncor_severity
Le 24/01/2024 à 11:38, Matthias Schiffer a écrit :
> [Vous ne recevez pas souvent de courriers de
> matthias.schif...@ew.tq-group.com. Découvrez pourquoi ceci est important à
> https://aka.ms/LearnAboutSenderIdentification ]
>
> MMU_FTR_USE_HIGH_BATS is set for G2_LE cores and derivatives
On 2024/1/25 21:47, Aneesh Kumar K.V wrote:
On 1/25/24 3:16 PM, Kunwu Chan wrote:
This part was commented in about 17 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu Chan
---
On Mon, 22 Jan 2024 22:43:05 -0800 Suren Baghdasaryan wrote:
> The change [1] missed ARM architecture when fixing major fault accounting
> for page fault retry under per-VMA lock. Add missing code to fix ARM
> architecture fault accounting.
>
> [1] 46e714c729c8 ("arch/mm/fault: fix major fault
This part was commented from commit a33a7d7309d7
("[PATCH] spufs: implement mfc access for PPE-side DMA")
in about 18 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu Chan
Suggested-by: Christophe Leroy
---
Changes
On Thu, Jan 25, 2024 at 03:55:06PM -0700, Nathan Chancellor wrote:
> Hi all,
>
> This series bumps the minimum supported version of LLVM for building the
> kernel to 13.0.1. The first patch does the bump and all subsequent
> patches clean up all the various workarounds and checks for earlier
>
On 2024/1/25 18:41, Christophe Leroy wrote:
Le 25/01/2024 à 11:08, Kunwu Chan a écrit :
This part was commented from commit a33a7d7309d7
("[PATCH] spufs: implement mfc access for PPE-side DMA")
in about 18 years before.
If there are no plans to enable this part code in the future,
we can
On Thu, Jan 25, 2024 at 6:04 PM Andrew Morton wrote:
>
> On Mon, 22 Jan 2024 22:43:05 -0800 Suren Baghdasaryan
> wrote:
>
> > The change [1] missed ARM architecture when fixing major fault accounting
> > for page fault retry under per-VMA lock. Add missing code to fix ARM
> > architecture fault
This part was commented in about 19 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu Chan
---
arch/powerpc/platforms/pseries/pci.c | 27 ---
1 file changed, 27 deletions(-)
diff --git
Christophe Leroy writes:
> Le 25/01/2024 à 17:33, Nathan Lynch a écrit :
>> Christophe Leroy writes:
>>> Hi Nathan,
>>>
>>> Le 06/03/2023 à 22:33, Nathan Lynch via B4 Relay a écrit :
From: Nathan Lynch
The kernel can handle retrying RTAS function calls in response to
Le 25/01/2024 à 17:33, Nathan Lynch a écrit :
> Christophe Leroy writes:
>> Hi Nathan,
>>
>> Le 06/03/2023 à 22:33, Nathan Lynch via B4 Relay a écrit :
>>> From: Nathan Lynch
>>>
>>> The kernel can handle retrying RTAS function calls in response to
>>> -2/990x in the sys_rtas() handler instead
On Thu, Jan 25, 2024 at 06:08:52AM -0600, Shivaprasad G Bhat wrote:
> On PPC64, the iommu_ops.def_domain_type() is not defined and
> CONFIG_IOMMU_DMA not enabled. With commit 0f6a90436a57 ("iommu: Do not
> use IOMMU_DOMAIN_DMA if CONFIG_IOMMU_DMA is not enabled"), the
>
Hi Nathan,
Le 06/03/2023 à 22:33, Nathan Lynch via B4 Relay a écrit :
> From: Nathan Lynch
>
> The kernel can handle retrying RTAS function calls in response to
> -2/990x in the sys_rtas() handler instead of relaying the intermediate
> status to user space.
From this series with still have
From: Baoquan He Sent: Thursday, January 25, 2024 1:17 AM
>
> On 01/25/24 at 05:12am, Michael Kelley wrote:
> > From: Baoquan He Sent: Wednesday, January 24, 2024
> 8:10 PM
> > >
> > > On 01/24/24 at 11:02pm, Michael Kelley wrote:
> > > > > diff --git a/arch/x86/kernel/cpu/mshyperv.c
> > > > >
On Thu, Jan 25, 2024 at 06:08:39AM -0600, Shivaprasad G Bhat wrote:
> The commit 2ad56efa80db ("powerpc/iommu: Setup a default domain and
> remove set_platform_dma_ops") refactored the code removing the
> set_platform_dma_ops(). It missed out the table group
> release_ownership() call which would
Christophe Leroy writes:
> Hi Nathan,
>
> Le 06/03/2023 à 22:33, Nathan Lynch via B4 Relay a écrit :
>> From: Nathan Lynch
>>
>> The kernel can handle retrying RTAS function calls in response to
>> -2/990x in the sys_rtas() handler instead of relaying the intermediate
>> status to user space.
>
During the kernel booting, the generic cpu_to_node() is called too early in
arm64, powerpc and riscv when CONFIG_NUMA is enabled.
There are at least four places in the common code where
the generic cpu_to_node() is called before it is initialized:
1.) early_trace_init() in
On 01/25/24 at 09:55pm, Nathan Chancellor wrote:
..
> I am seeing a few build failures in my test matrix on next-20240125 that
> appear to be caused by this series although I have not bisected. Some
> reproduction steps:
Thanks for trying this, I have reproduced the linking failu
AX_MEMORY_RANGES=8192
> # end of Kexec and crash features
> ---
>
> (3) unset CONFIG_CRASH_DUMP in case 2 and execute 'make olddefconfig':
>
> # Kexec and crash features
> CONFIG_KEXEC_CORE=y
> CONFIG_KEXEC_FILE=y
> # end of Kexe
On Fri, Jan 26, 2024, at 03:12, Kunwu Chan wrote:
> This part was commented from commit a33a7d7309d7
> ("[PATCH] spufs: implement mfc access for PPE-side DMA")
> in about 18 years before.
>
> If there are no plans to enable this part code in the future,
> we can remove this dead code.
>
>
We want to make use of pte_next_pfn() outside of set_ptes(). Let's
simply define PFN_PTE_SHIFT, required by pte_next_pfn().
Signed-off-by: David Hildenbrand
---
arch/nios2/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/nios2/include/asm/pgtable.h
We want to make use of pte_next_pfn() outside of set_ptes(). Let's
simply define PFN_PTE_SHIFT, required by pte_next_pfn().
Signed-off-by: David Hildenbrand
---
arch/powerpc/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/include/asm/pgtable.h
Let's provide pte_next_pfn(), independently of set_ptes(). This allows for
using the generic pte_next_pfn() version in some arch-specific set_ptes()
implementations, and prepares for reusing pte_next_pfn() in other context.
Signed-off-by: David Hildenbrand
---
include/linux/pgtable.h | 2 +-
1
From: Gaurav Batra
When kdump kernel tries to copy dump data over SR-IOV, LPAR panics due to
NULL pointer execption.
Here is the complete stack
[ 19.944378] Kernel attempted to read user page (0) - exploit attempt? (uid:
0)^M
[ 19.944388] BUG: Kernel NULL pointer dereference on read at
Le 25/01/2024 à 20:32, David Hildenbrand a écrit :
> Let's provide pte_next_pfn(), independently of set_ptes(). This allows for
> using the generic pte_next_pfn() version in some arch-specific set_ptes()
> implementations, and prepares for reusing pte_next_pfn() in other context.
>
>
Hi,
Le 06/06/2020 à 06:45, Sourabh Jain a écrit :
When we hit the fadump crash via the panic path the pstore update is
missing. This is observed when commit 8341f2f222d7 ("sysrq: Use panic()
to force a crash") changed the sysrq-trigger to take panic path instead
of die path.
The PPC panic
Le 18/04/2022 à 06:38, Shivaprasad G Bhat a écrit :
> papr_scm and ndtest share common PDSM payload structs like
> nd_papr_pdsm_health. Presently these structs are duplicated across
> papr_pdsm.h and ndtest.h header files. Since 'ndtest' is essentially
> arch independent and can run on platforms
From: Ryan Roberts
Since the high bits [51:48] of an OA are not stored contiguously in the
PTE, there is a theoretical bug in set_ptes(), which just adds PAGE_SIZE
to the pte to get the pte with the next pfn. This works until the pfn
crosses the 48-bit boundary, at which point we overflow into
We want to make use of pte_next_pfn() outside of set_ptes(). Let's
simply define PFN_PTE_SHIFT, required by pte_next_pfn().
Signed-off-by: David Hildenbrand
---
arch/arm/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/pgtable.h
Let's use our handy helper now that it's available on all archs.
Signed-off-by: David Hildenbrand
---
arch/arm/mm/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 674ed71573a84..c24e29c0b9a48 100644
--- a/arch/arm/mm/mmu.c
+++
Let's use our handy new helper. Note that the implementation is slightly
different, but shouldn't really make a difference in practice.
Signed-off-by: David Hildenbrand
---
arch/powerpc/mm/pgtable.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
Hi,
Le 22/05/2018 à 10:23, Pingfan Liu a écrit :
> For kexec -p, the boot cpu can be not the cpu0, this causes the problem
> to alloc paca[]. In theory, there is no requirement to assign cpu's logical
> id as its present seq by device tree. But we have something like
> cpu_first_thread_sibling(),
Hi Nic,
Le 21/05/2017 à 03:01, Nicholas Piggin a écrit :
Implement build-time fixup of alternate feature relative addresses for
the out-of-line ("else") patch code. This is done post-link with a new
powerpc build tool that parses relocations and fixup structures, and
adjusts branch
Now that the rmap overhaul[1] is upstream that provides a clean interface
for rmap batching, let's implement PTE batching during fork when processing
PTE-mapped THPs.
This series is partially based on Ryan's previous work[2] to implement
cont-pte support on arm64, but its a complete rewrite based
We want to make use of pte_next_pfn() outside of set_ptes(). Let's
simply define PFN_PTE_SHIFT, required by pte_next_pfn().
Signed-off-by: David Hildenbrand
---
arch/s390/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/s390/include/asm/pgtable.h
We want to make use of pte_next_pfn() outside of set_ptes(). Let's
simply define PFN_PTE_SHIFT, required by pte_next_pfn().
Signed-off-by: David Hildenbrand
---
arch/sparc/include/asm/pgtable_64.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/sparc/include/asm/pgtable_64.h
We want to make use of pte_next_pfn() outside of set_ptes(). Let's
simply define PFN_PTE_SHIFT, required by pte_next_pfn().
Reviewed-by: Alexandre Ghiti
Signed-off-by: David Hildenbrand
---
arch/riscv/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
We already read it, let's just forward it.
This patch is based on work by Ryan Roberts.
Reviewed-by: Ryan Roberts
Signed-off-by: David Hildenbrand
---
mm/memory.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/mm/memory.c b/mm/memory.c
index
Let's prepare for further changes.
Reviewed-by: Ryan Roberts
Signed-off-by: David Hildenbrand
---
mm/memory.c | 63 -
1 file changed, 33 insertions(+), 30 deletions(-)
diff --git a/mm/memory.c b/mm/memory.c
index 7e1f4849463aa..10fc14ff8e49b
Let's implement PTE batching when consecutive (present) PTEs map
consecutive pages of the same large folio, and all other PTE bits besides
the PFNs are equal.
We will optimize folio_pte_batch() separately, to ignore selected
PTE bits. This patch is based on work by Ryan Roberts.
Use
Let's always ignore the accessed/young bit: we'll always mark the PTE
as old in our child process during fork, and upcoming users will
similarly not care.
Ignore the dirty bit only if we don't want to duplicate the dirty bit
into the child process during fork. Maybe, we could just set all PTEs
in
... and conditionally return to the caller if any PTE except the first one
is writable. fork() has to make sure to properly write-protect in case any
PTE is writable. Other users (e.g., page unmaping) are expected to not
care.
Reviewed-by: Ryan Roberts
Signed-off-by: David Hildenbrand
---
Le 25/01/2024 à 20:32, David Hildenbrand a écrit :
> We want to make use of pte_next_pfn() outside of set_ptes(). Let's
> simply define PFN_PTE_SHIFT, required by pte_next_pfn().
>
> Signed-off-by: David Hildenbrand
Reviewed-by: Christophe Leroy
> ---
> arch/powerpc/include/asm/pgtable.h
Le 25/01/2024 à 20:32, David Hildenbrand a écrit :
> Let's use our handy new helper. Note that the implementation is slightly
> different, but shouldn't really make a difference in practice.
>
> Signed-off-by: David Hildenbrand
Reviewed-by: Christophe Leroy
> ---
>
Hi all,
This series bumps the minimum supported version of LLVM for building the
kernel to 13.0.1. The first patch does the bump and all subsequent
patches clean up all the various workarounds and checks for earlier
versions.
Quoting the first patch's commit message for those that were only on
This reverts commit 6fcb574125e6 ("powerpc: Kconfig: disable
CONFIG_COMPAT for clang < 12").
Now that the minimum supported version of LLVM for building the kernel
has been bumped to 13.0.1, this condition is always true, as the build
will fail during the configuration stage for older LLVM
This part was commented from commit 165785e5c0be ("[POWERPC] Cell
iommu support") in about 17 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu Chan
---
Change in v2:
- Remove the second blank line
---
This part was commented from commit 2f4cf5e42d13 ("Add book3s.c")
in about 14 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu Chan
---
Change in v2:
- Remove redundant blank line
---
arch/powerpc/kvm/book3s.c | 4
On 2024/1/24 21:01, Christophe Leroy wrote:
Le 24/01/2024 à 10:36, Kunwu Chan a écrit :
This part was commented from commit 2f4cf5e42d13 ("Add book3s.c")
in about 14 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
Signed-off-by: Kunwu
在 2024/1/25 15:31, Mike Rapoport 写道:
On Wed, Jan 24, 2024 at 09:19:00AM -0800, Lameter, Christopher wrote:
On Tue, 23 Jan 2024, Huang Shijie wrote:
During the kernel booting, the generic cpu_to_node() is called too early in
arm64, powerpc and riscv when CONFIG_NUMA is enabled.
For
On 01/25/24 at 05:12am, Michael Kelley wrote:
> From: Baoquan He Sent: Wednesday, January 24, 2024 8:10 PM
> >
> > On 01/24/24 at 11:02pm, Michael Kelley wrote:
> > > > diff --git a/arch/x86/kernel/cpu/mshyperv.c
> > > > b/arch/x86/kernel/cpu/mshyperv.c
> > > > index 01fa06dd06b6..f8163a59026b
On 2024/1/25 14:49, Christophe Leroy wrote:
Le 25/01/2024 à 03:46, Kunwu Chan a écrit :
This part was commented from commit 165785e5c0be ("[POWERPC] Cell
iommu support") in about 17 years before.
If there are no plans to enable this part code in the future,
we can remove this dead code.
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