[PATCH] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-02-27 Thread Athira Rajeev
r 64-bit book3s") Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 3086055..48b61cc 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/ar

[PATCH v2] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-03-13 Thread Athira Rajeev
rently all of the bits from SIER are saved for EBB events. Patch fixes this by ANDing the "sier_user_mask" to data from SIER in ebb_switch_out(). This will force save only architected bits from the SIER. Fixes: 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit book3s"

Re: [PATCH v3] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-03-27 Thread Athira Rajeev
> On 19-Mar-2020, at 4:22 PM, Michael Ellerman wrote: > > Hi Athira, > > Athira Rajeev writes: >> Sampled Instruction Event Register (SIE

[PATCH v2] powerpc/perf: Add documentation around use of "ppc_set_pmu_inuse" in PMU core-book3s

2020-03-31 Thread Athira Rajeev
e VPA flag "pmcregs_in_use". "pmcregs_in_use" flag is set in "power_pmu_enable" via ppc_set_pmu_inuse(1) and it is unset when there are no active events (n_events == 0 condition). Patch here adds documentation on the ppc_set_pmu_inuse() usage. Signed-off-by: Madhavan

Re: [PATCH] powerpc/perf: Add documentation around use of "ppc_set_pmu_inuse" in PMU core-book3s

2020-03-31 Thread Athira Rajeev
Hi, Please ignore this version as I messed up with the author information. I am sending a V2 with the proper author name. Thanks Athira > On 30-Mar-2020, at 5:08 PM, Athira Rajeev wrote: > > "pmcregs_in_use" flag is part of lppaca (Virtual Process Area), > which is us

[PATCH] powerpc/perf: Add documentation around use of "ppc_set_pmu_inuse" in PMU core-book3s

2020-03-30 Thread Athira Rajeev
ot;. "pmcregs_in_use" flag is set in "power_pmu_enable" via ppc_set_pmu_inuse(1) and it is unset when there are no active events (n_events == 0 condition). Patch here adds documentation on the ppc_set_pmu_inuse() usage. Signed-off-by: Madhavan Srinivasan Signed-off-by: At

[PATCH V2] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-05-19 Thread Athira Rajeev
0x1e00 mmcr2 0x0 ... thread: perf:4784 Signed-off-by: Anju T Sudhakar [Defined PERF_REG_EXTENDED_MASK at run time to add support for different platforms ] Signed-off-by: Athira Rajeev --- Changes from v1 -> v2 - PERF_REG_EXTENDED_MASK` is defined at runtime in the kernel based on platf

Re: [PATCH 2/2] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-05-06 Thread Athira Rajeev
> On 06-May-2020, at 9:56 AM, Madhavan Srinivasan wrote: > > > > On 4/29/20 11:34 AM, Anju T Sudhakar wrote: >> The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the >> PMU which support extended registers. The generic code define the mask >> of extended registers as 0 for

Re: [PATCH v2] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-03-18 Thread Athira Rajeev
> On 13-Mar-2020, at 11:36 PM, Segher Boessenkool > wrote: > > On Fri, Mar 13, 2020 at 01:49:07PM -0400, Athira Rajeev wrote: >> Sampled instruction address register (SIER), is a PMU register, > > SIER stands for "Sampled Instruction Event Register", instea

[PATCH v3] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-03-18 Thread Athira Rajeev
rently all of the bits from SIER are saved for EBB events. Patch fixes this by ANDing the "sier_user_mask" to data from SIER in ebb_switch_out(). This will force save only architected bits from the SIER. Fixes: 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit book3s"

[PATCH 0/4] powerpc/perf: Power PMU fixes for power10 DD1

2020-10-08 Thread Athira Rajeev
userspace profiling. Athira Rajeev (4): powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" for power10 DD1 powerpc/perf: Using SIER[CMPL] instead of SIER[SIAR_VALID] powerpc/perf: Use the address from SIAR register to set cpumode flags powerpc/perf: Exclude kernel samples whil

[PATCH 1/4] powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" for power10 DD1

2020-10-08 Thread Athira Rajeev
Add a new power PMU flag "PPMU_P10_DD1" which can be used to conditionally add any code path for power10 DD1 processor version. Also modify power10 PMU driver code to set this flag only for DD1, based on the Processor Version Register (PVR) value. Signed-off-by: Athira Rajeev --- ar

[PATCH 3/4] powerpc/perf: Use the address from SIAR register to set cpumode flags

2020-10-08 Thread Athira Rajeev
. Hence add a check to use the address in Sampled Instruction Address Register (SIAR) to identify the privilege level. Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc

[PATCH 4/4] powerpc/perf: Exclude kernel samples while counting events in user space.

2020-10-08 Thread Athira Rajeev
). Patch adds a check to drop these samples at such conditions. Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 12 1 file changed, 12 insertions(+) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index c018004..10a2d1f 100644 --- a/arch

[PATCH 2/4] powerpc/perf: Using SIER[CMPL] instead of SIER[SIAR_VALID]

2020-10-08 Thread Athira Rajeev
is set. So add a condition check for power10 DD1 to use SIER[CMPL] bit instead. Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index

[PATCH] powerpc/perf: Fix reading of MSR[HV PR] bits in trace-imc

2020-08-26 Thread Athira Rajeev
;) Signed-off-by: Athira Rajeev --- arch/powerpc/perf/imc-pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index a45d694..62d0b54 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -1

Re: [PATCH -next v2] powerpc/perf: Fix symbol undeclared warning

2020-09-23 Thread Athira Rajeev
bol 'p9_dd21_bl_ev' > was not declared. Should it be static? > arch/powerpc/perf/power9-pmu.c:115:5: warning: symbol 'p9_dd22_bl_ev' > was not declared. Should it be static? > > Those symbols are used only in the files that define them so we declare > them as static to fix the warnings. Hi, Loo

Re: [PATCH V2] powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints

2020-09-23 Thread Athira Rajeev
> On 22-Sep-2020, at 4:16 PM, Paul A. Clarke wrote: > > Just one nit in a comment below... > (and this is not worthy of tags like "reviewed-by" ;-) > > On Mon, Sep 21, 2020 at 03:10:04AM -0400, Athira Rajeev wrote: >> PMU counter support functions en

Re: [PATCH -next] powerpc/perf: Fix symbol undeclared warning

2020-09-22 Thread Athira Rajeev
> On 21-Sep-2020, at 4:55 PM, Wang Wensheng wrote: > > Build kernel with `C=2`: > arch/powerpc/perf/isa207-common.c:24:18: warning: symbol > 'isa207_pmu_format_attr' was not declared. Should it be static? > arch/powerpc/perf/power9-pmu.c:101:5: warning: symbol 'p9_dd21_bl_ev' > was not

Re: [PATCH v2 6/7] powerpc/perf: Remove unused variable 'target' in trace_imc_event_init()

2020-09-17 Thread Athira Rajeev
ent_init(struct perf_event > *event) > mutex_unlock(_global_refc.lock); > > event->hw.idx = -1; > - target = event->hw.target; Reviewed-by: Athira Rajeev Thanks Athira > > event->pmu->task_ctx_nr = perf_hw_context; > event->destroy = reset_global_refc; > -- > 2.25.4 >

Re: [PATCH] powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints

2020-09-17 Thread Athira Rajeev
> On 17-Sep-2020, at 5:43 PM, Michael Ellerman wrote: > > Athira Rajeev writes: >> PMU counter support functions enforces event constraints for group of >> events to check if all events in a group can be monitored. Incase of >> event codes using PMC5 and PMC6 ( 5

[PATCH V4 2/2] tools/perf: Add perf tools support for extended register capability in powerpc

2020-05-27 Thread Athira Rajeev
sample. Hence decide the mask value based on the processor version. Signed-off-by: Anju T Sudhakar [Decide extended mask at run time based on platform] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan --- tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++- tools/perf/arch

[PATCH V4 1/2] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-05-27 Thread Athira Rajeev
mmcr0 0x82008090 mmcr1 0x1e00 mmcr2 0x0 ... thread: perf:4784 Signed-off-by: Anju T Sudhakar [Defined PERF_REG_EXTENDED_MASK at run time to add support for different platforms ] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan --- arch/powerpc/include/asm

[PATCH V4 0/2] powerpc/perf: Add support for perf extended regs in powerpc

2020-05-27 Thread Athira Rajeev
Patch set to add support for perf extended register capability in powerpc. The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the PMU which support extended registers. The generic code define the mask of extended registers as 0 for non supported architectures. patch 1/2 defines

[PATCH V3 0/2] powerpc/perf: Add support for perf extended regs in powerpc

2020-05-20 Thread Athira Rajeev
Patch set to add support for perf extended register capability in powerpc. The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the PMU which support extended registers. The generic code define the mask of extended registers as 0 for non supported architectures. patch 1/2 defines

[PATCH V3 1/2] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-05-20 Thread Athira Rajeev
mmcr0 0x82008090 mmcr1 0x1e00 mmcr2 0x0 ... thread: perf:4784 Signed-off-by: Anju T Sudhakar [Defined PERF_REG_EXTENDED_MASK at run time to add support for different platforms ] Signed-off-by: Athira Rajeev --- arch/powerpc/include/asm/perf_event_server.h | 8 +++ arch

[PATCH V3 2/2] tools/perf: Add perf tools support for extended register capability in powerpc

2020-05-20 Thread Athira Rajeev
sample. Hence decide the mask value based on the processor version. Signed-off-by: Anju T Sudhakar [Decide extended mask at run time based on platform] Signed-off-by: Athira Rajeev --- tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++- tools/perf/arch/powerpc/include/perf_regs.h

[PATCH] powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints

2020-09-16 Thread Athira Rajeev
: 7ffd948 ('powerpc/perf: factor out power8 pmu functions') Signed-off-by: Athira Rajeev --- arch/powerpc/perf/isa207-common.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c index 964437a..186fad8 100644 --- a/arch

[PATCH V2] powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints

2020-09-21 Thread Athira Rajeev
: 7ffd948 ("powerpc/perf: factor out power8 pmu functions") Signed-off-by: Athira Rajeev --- Changes in v2: - Added a block comment in the fix path explaining why the change is needed. arch/powerpc/perf/isa207-common.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/ar

Re: [v3 01/15] powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers

2020-07-21 Thread Athira Rajeev
> On 21-Jul-2020, at 9:12 AM, Jordan Niethe wrote: > > On Sat, Jul 18, 2020 at 12:48 AM Athira Rajeev > mailto:atraj...@linux.vnet.ibm.com>> wrote: >> >> core-book3s currently uses array to store the MMCR registers as part >> of per-cpu `cpu_hw_events

Re: [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR

2020-07-21 Thread Athira Rajeev
> On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote: > > On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote: >> Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers >> in a flat array in order: mmcr0, mmcr1, mmcra, mmcr2, mmcrs >> Split this

Re: [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR

2020-07-22 Thread Athira Rajeev
> On 22-Jul-2020, at 10:07 AM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: >>> On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote: >>> On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote: >>>&

Re: [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-22 Thread Athira Rajeev
> On 22-Jul-2020, at 4:19 PM, Jordan Niethe wrote: > > On Wed, Jul 22, 2020 at 5:55 PM Athira Rajeev > mailto:atraj...@linux.vnet.ibm.com>> wrote: >> >> >> >> On 22-Jul-2020, at 10:11 AM, Jordan Niethe wrote: >> >> On Sat, Jul 18, 20

Re: [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-22 Thread Athira Rajeev
> On 22-Jul-2020, at 10:11 AM, Jordan Niethe wrote: > > On Sat, Jul 18, 2020 at 1:13 AM Athira Rajeev > mailto:atraj...@linux.vnet.ibm.com>> wrote: >> >> From: Madhavan Srinivasan >> >> Add power10 feature function to dt_cpu_ftrs.c along >>

Re: [v3 04/15] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-07-22 Thread Athira Rajeev
> On 22-Jul-2020, at 9:48 AM, Jordan Niethe wrote: > > On Sat, Jul 18, 2020 at 1:02 AM Athira Rajeev > mailto:atraj...@linux.vnet.ibm.com>> wrote: >> >> From: Madhavan Srinivasan >> >> PowerISA v3.1 includes new performance monitoring un

Re: [PATCH V5 0/4] powerpc/perf: Add support for perf extended regs in powerpc

2020-07-30 Thread Athira Rajeev
> On 27-Jul-2020, at 10:46 PM, Athira Rajeev > wrote: > > Patch set to add support for perf extended register capability in > powerpc. The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to > indicate the PMU which support extended registers. The generic code

Re: [PATCH V5 0/4] powerpc/perf: Add support for perf extended regs in powerpc

2020-08-06 Thread Athira Rajeev
> On 06-Aug-2020, at 5:50 PM, Arnaldo Carvalho de Melo wrote: > > Em Fri, Jul 31, 2020 at 11:04:14PM +0530, Athira Rajeev escreveu: >> >> >>> On 31-Jul-2020, at 1:20 AM, Jiri Olsa wrote: >>> >>> On Thu, Jul 30, 2020 at 01:24:40PM +0530,

[PATCH V6 1/2] tools/perf: Add perf tools support for extended register capability in powerpc

2020-08-07 Thread Athira Rajeev
extended mask at run time based on platform] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan Reviewed-by: Kajol Jain Reviewed-and-tested-by: Ravi Bangoria --- tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++- tools/perf/arch/powerpc/include/perf_regs.h | 5 ++- tools

[PATCH V6 0/2] powerpc/perf: Add support for perf extended regs in powerpc

2020-08-07 Thread Athira Rajeev
d support for outputting extended regs in perf intr_regs Athira Rajeev (1): powerpc/perf: Add extended regs support for power10 platform arch/powerpc/include/asm/perf_event.h| 3 ++ arch/powerpc/include/asm/perf_event_server.h | 5 arch/powerpc/include/uapi/asm/perf_regs.

[PATCH V6 2/2] powerpc/perf: Add extended regs support for power10 platform

2020-08-07 Thread Athira Rajeev
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10 and expose MMCR3, SIER2, SIER3 registers as part of extended regs. Also introduce `PERF_REG_PMU_MASK_31` to define extended mask value at runtime for power10 Signed-off-by: Athira Rajeev [Fix build failure on PPC32 platform

[PATCH V6 0/2] tools/perf: Add extended regs support for powerpc

2020-08-07 Thread Athira Rajeev
from Ravi Bangoria to initialize `perf_reg_extended_max` and define it in lowercase since it is local variable. Anju T Sudhakar (1): tools/perf: Add perf tools support for extended register capability in powerpc Athira Rajeev (1): tools/perf: Add perf tools support for extended regs i

[PATCH V6 1/2] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-08-07 Thread Athira Rajeev
mmcr0 0x82008090 mmcr1 0x1e00 mmcr2 0x0 ... thread: perf:4784 Signed-off-by: Anju T Sudhakar [Defined PERF_REG_EXTENDED_MASK at run time to add support for different platforms ] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan [Fix build issue using

[PATCH V6 2/2] tools/perf: Add perf tools support for extended regs in power10

2020-08-07 Thread Athira Rajeev
Added support for supported regs which are new in power10 ( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side to use with `-I?` option. Also added PVR check to send extended mask for power10 at kernel while capturing extended regs in each sample. Signed-off-by: Athira Rajeev Reviewed

Re: [PATCH V5 0/4] powerpc/perf: Add support for perf extended regs in powerpc

2020-07-31 Thread Athira Rajeev
> On 31-Jul-2020, at 1:20 AM, Jiri Olsa wrote: > > On Thu, Jul 30, 2020 at 01:24:40PM +0530, Athira Rajeev wrote: >> >> >>> On 27-Jul-2020, at 10:46 PM, Athira Rajeev >>> wrote: >>> >>> Patch set to add support for perf extende

[PATCH] powerpc/perf: Account for interrupts during PMC overflow for an invalid SIAR check

2020-08-06 Thread Athira Rajeev
is more than max_samples_per_tick. This leads to soft lockup. Fix this by adding perf_event_account_interrupt in the invalid siar code path for a sampling event. ie if siar is invalid, just do interrupt check and don't record the sample information. Signed-off-by: Athira Rajeev Reported-by: Alexey

[PATCH v2 00/10] powerpc/perf: Add support for power10 PMU Hardware

2020-07-01 Thread Athira Rajeev
The patch series adds support for power10 PMU hardware. Anju T Sudhakar (2): powerpc/perf: Add support for outputting extended regs in perf intr_regs tools/perf: Add perf tools support for extended register capability in powerpc Athira Rajeev (5): KVM: PPC: Book3S HV: Save/restore

[PATCH v2 10/10] powerpc/perf: Add extended regs support for power10 platform

2020-07-01 Thread Athira Rajeev
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10 and expose MMCR3, SIER2, SIER3 registers as part of extended regs. Also introduce `PERF_REG_PMU_MASK_31` to define extended mask value at runtime for power10 Signed-off-by: Athira Rajeev --- arch/powerpc/include/uapi/asm

[PATCH v2 04/10] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-01 Thread Athira Rajeev
From: Madhavan Srinivasan Add power10 feature function to dt_cpu_ftrs.c along with a power10 specific init() to initialize pmu sprs. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/include/asm/reg.h| 3 +++ arch/powerpc/kernel/cpu_setup_power.S | 7 +++

[PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes

2020-07-01 Thread Athira Rajeev
processors, since PowerISA v3.1 allows only MSR[PR]=1 address to be written to BHRB buffer. Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 27 +-- arch/powerpc/perf/isa207-common.c | 13 + arch/powerpc/perf/power10-pmu.c |

[PATCH v2 03/10] powerpc/xmon: Add PowerISA v3.1 PMU SPRs

2020-07-01 Thread Athira Rajeev
From: Madhavan Srinivasan PowerISA v3.1 added three new perfromance monitoring unit (PMU) speical purpose register (SPR). They are Monitor Mode Control Register 3 (MMCR3), Sampled Instruction Event Register 2 (SIER2), Sampled Instruction Event Register 3 (SIER3). Patch here adds a new dump

[PATCH v2 09/10] tools/perf: Add perf tools support for extended register capability in powerpc

2020-07-01 Thread Athira Rajeev
sample. Hence decide the mask value based on the processor version. Signed-off-by: Anju T Sudhakar [Decide extended mask at run time based on platform] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan --- tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++- tools/perf/arch

[PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-07-01 Thread Athira Rajeev
From: Madhavan Srinivasan PowerISA v3.1 includes new performance monitoring unit(PMU) special purpose registers (SPRs). They are Monitor Mode Control Register 3 (MMCR3) Sampled Instruction Event Register 2 (SIER2) Sampled Instruction Event Register 3 (SIER3) MMCR3 is added for further sampling

[PATCH v2 02/10] KVM: PPC: Book3S HV: Save/restore new PMU registers

2020-07-01 Thread Athira Rajeev
entering/exiting guest. Signed-off-by: Athira Rajeev --- arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +- arch/powerpc/include/asm/kvm_host.h | 4 ++-- arch/powerpc/kernel/asm-offsets.c | 3 +++ arch/powerpc/kvm/book3s_hv.c | 6 -- arch/powerpc/kvm

[PATCH v2 08/10] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-07-01 Thread Athira Rajeev
mmcr0 0x82008090 mmcr1 0x1e00 mmcr2 0x0 ... thread: perf:4784 Signed-off-by: Anju T Sudhakar [Defined PERF_REG_EXTENDED_MASK at run time to add support for different platforms ] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan --- arch/powerpc/include/asm

[PATCH v2 05/10] powerpc/perf: Update Power PMU cache_events to u64 type

2020-07-01 Thread Athira Rajeev
nts. Signed-off-by: Athira Rajeev --- arch/powerpc/include/asm/perf_event_server.h | 2 +- arch/powerpc/perf/core-book3s.c | 2 +- arch/powerpc/perf/generic-compat-pmu.c | 2 +- arch/powerpc/perf/mpc7450-pmu.c | 2 +- arch/powerpc/perf/power5+-pmu.c | 2 +- a

[PATCH v2 06/10] powerpc/perf: power10 Performance Monitoring support

2020-07-01 Thread Athira Rajeev
the support function in isa207_common.c to include power10 pmu hardware. [Enablement of base PMU driver code] Signed-off-by: Madhavan Srinivasan [Addition of ISA macros for counter support functions] Signed-off-by: Athira Rajeev --- arch/powerpc/perf/Makefile | 2 +- arch/powerpc

Re: [PATCH v2 04/10] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-07 Thread Athira Rajeev
> On 07-Jul-2020, at 11:52 AM, Michael Neuling wrote: > > On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote: >> From: Madhavan Srinivasan >> >> Add power10 feature function to dt_cpu_ftrs.c along >> with a power10 specific init() to initialize pmu

Re: [PATCH v2 10/10] powerpc/perf: Add extended regs support for power10 platform

2020-07-07 Thread Athira Rajeev
plied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use as documented in > https://git-scm.com/docs/git-format-patch] > > url: > https://github.com/0day-ci/linux/commits/Athira-Rajeev/powerpc-perf-Add-support-for-power10-PMU-Hardware/202007

Re: [PATCH v2 10/10] powerpc/perf: Add extended regs support for power10 platform

2020-07-09 Thread Athira Rajeev
> On 08-Jul-2020, at 5:34 PM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: >> Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10 >> and expose MMCR3, SIER2, SIER3 registers as part of ex

Re: [PATCH v2 04/10] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-09 Thread Athira Rajeev
> On 08-Jul-2020, at 4:45 PM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: >> From: Madhavan Srinivasan >> >> Add power10 feature function to dt_cpu_ftrs.c along >> with a power10 specific init()

Re: [PATCH v2 06/10] powerpc/perf: power10 Performance Monitoring support

2020-07-08 Thread Athira Rajeev
> On 07-Jul-2020, at 12:20 PM, Michael Neuling wrote: > > >> @@ -480,6 +520,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev, >> mmcr[1] = mmcr1; >> mmcr[2] = mmcra; >> mmcr[3] = mmcr2; >> +mmcr[4] = mmcr3; > > This is fragile like the kvm vcpu case I commented on

Re: [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes

2020-07-08 Thread Athira Rajeev
> On 07-Jul-2020, at 12:47 PM, Michael Neuling wrote: > > On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote: >> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). >> First is the addition of BHRB disable bit and second new filtering >>

Re: [PATCH v3] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-07-15 Thread Athira Rajeev
> On 14-Jul-2020, at 11:38 AM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: >>> On 19-Mar-2020, at 4:22 PM, Michael Ellerman wrote: >>> >>> Hi Athira, >>> >>> Athira Rajeev writes: &g

Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-07-15 Thread Athira Rajeev
> On 13-Jul-2020, at 6:20 PM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: >>> On 08-Jul-2020, at 4:32 PM, Michael Ellerman wrote: >>> >>> Athira Rajeev writes: >>> ... >>>> diff

Re: [PATCH v2 09/10] tools/perf: Add perf tools support for extended register capability in powerpc

2020-07-12 Thread Athira Rajeev
> On 08-Jul-2020, at 5:34 PM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: >> From: Anju T Sudhakar >> >> Add extended regs to sample_reg_mask in the tool side to use >> with `-I?` option. Per

Re: [PATCH v2 02/10] KVM: PPC: Book3S HV: Save/restore new PMU registers

2020-07-02 Thread Athira Rajeev
> On 01-Jul-2020, at 4:41 PM, Paul Mackerras wrote: > > On Wed, Jul 01, 2020 at 05:20:54AM -0400, Athira Rajeev wrote: >> PowerISA v3.1 has added new performance monitoring unit (PMU) >> special purpose registers (SPRs). They are >> >> Monitor Mode Cont

Re: [PATCH v2 03/10] powerpc/xmon: Add PowerISA v3.1 PMU SPRs

2020-07-08 Thread Athira Rajeev
> On 08-Jul-2020, at 4:34 PM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: >> From: Madhavan Srinivasan >> >> PowerISA v3.1 added three new perfromance >> monitoring unit (PMU) speical purpose regist

Re: [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes

2020-07-08 Thread Athira Rajeev
> On 08-Jul-2020, at 1:13 PM, Gautham R Shenoy wrote: > > On Tue, Jul 07, 2020 at 05:17:55PM +1000, Michael Neuling wrote: >> On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote: >>> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). >>&

Re: [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes

2020-07-08 Thread Athira Rajeev
> On 08-Jul-2020, at 5:12 PM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: > >> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). > ^ > a >> Fi

Re: [PATCH v2 09/10] tools/perf: Add perf tools support for extended register capability in powerpc

2020-07-08 Thread Athira Rajeev
> On 08-Jul-2020, at 5:34 PM, Michael Ellerman wrote: > > Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes: >> From: Anju T Sudhakar >> >> Add extended regs to sample_reg_mask in the tool side to use >> with `-I?` option. Per

Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-07-08 Thread Athira Rajeev
> On 08-Jul-2020, at 4:32 PM, Michael Ellerman wrote: > > Athira Rajeev writes: > ... >> diff --git a/arch/powerpc/perf/core-book3s.c >> b/arch/powerpc/perf/core-book3s.c >> index cd6a742..5c64bd3 100644 >> --- a/arch/powerpc/perf/core-book3s.c >

[PATCH 1/7] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-06-05 Thread Athira Rajeev
From: Madhavan Srinivasan PowerISA v3.1 includes new performance monitoring unit(PMU) special purpose registers (SPRs). They are Monitor Mode Control Register 3 (MMCR3) Sampled Instruction Event Register 2 (SIER2) Sampled Instruction Event Register 3 (SIER3) MMCR3 is added for further sampling

[PATCH 0/7] powerpc/perf: Add support for power10 PMU Hardware

2020-06-05 Thread Athira Rajeev
The patch series adds support for power10 PMU hardware. And code changes are based on powerpc/next. Athira Rajeev (4): KVM: PPC: Book3S HV: Save/restore new PMU registers powerpc/perf: Update Power PMU cache_events to u64 type powerpc/perf: power10 Performance Monitoring support powerpc

[PATCH 3/7] powerpc/xmon: Add PowerISA v3.1 PMU SPRs

2020-06-05 Thread Athira Rajeev
From: Madhavan Srinivasan PowerISA v3.1 added three new perfromance monitoring unit (PMU) speical purpose register (SPR). They are Monitor Mode Control Register 3 (MMCR3), Sampled Instruction Event Register 2 (SIER2), Sampled Instruction Event Register 3 (SIER3). Patch here adds a new dump

[PATCH 7/7] powerpc/perf: support BHRB disable bit and new filtering modes

2020-06-05 Thread Athira Rajeev
processors, since PowerISA v3.1 allows only MSR[PR]=1 address to be written to BHRB buffer. Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 27 +-- arch/powerpc/perf/isa207-common.c | 13 + arch/powerpc/perf/power10-pmu.c |

[PATCH 5/7] powerpc/perf: Update Power PMU cache_events to u64 type

2020-06-05 Thread Athira Rajeev
nts. Signed-off-by: Athira Rajeev --- arch/powerpc/include/asm/perf_event_server.h | 2 +- arch/powerpc/perf/core-book3s.c | 2 +- arch/powerpc/perf/generic-compat-pmu.c | 2 +- arch/powerpc/perf/mpc7450-pmu.c | 2 +- arch/powerpc/perf/power5+-pmu.c | 2 +- a

[PATCH 4/7] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-06-05 Thread Athira Rajeev
From: Madhavan Srinivasan Add power10 feature function to dt_cpu_ftrs.c along with a power10 specific init() to initialize pmu sprs. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/include/asm/reg.h| 3 +++ arch/powerpc/kernel/cpu_setup_power.S | 7 +++

[PATCH 2/7] KVM: PPC: Book3S HV: Save/restore new PMU registers

2020-06-05 Thread Athira Rajeev
entering/exiting guest. Signed-off-by: Athira Rajeev --- arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +- arch/powerpc/include/asm/kvm_host.h | 4 ++-- arch/powerpc/kernel/asm-offsets.c | 3 +++ arch/powerpc/kvm/book3s_hv.c | 6 -- arch/powerpc/kvm

[PATCH 6/7] powerpc/perf: power10 Performance Monitoring support

2020-06-05 Thread Athira Rajeev
the support function in isa207_common.c to include power10 pmu hardware. [Enablement of base PMU driver code] Signed-off-by: Madhavan Srinivasan [Addition of ISA macros for counter support functions] Signed-off-by: Athira Rajeev --- arch/powerpc/perf/Makefile | 2 +- arch/powerpc

Re: [v3 13/15] tools/perf: Add perf tools support for extended register capability in powerpc

2020-07-24 Thread Athira Rajeev
> On 24-Jul-2020, at 4:32 PM, Ravi Bangoria wrote: > > Hi Athira, > > On 7/17/20 8:08 PM, Athira Rajeev wrote: >> From: Anju T Sudhakar >> Add extended regs to sample_reg_mask in the tool side to use >> with `-I?` option. Perf tools side uses extende

[v4] powerpc/perf: Initialize power10 PMU registers in cpu setup routine

2020-07-23 Thread Athira Rajeev
re at boot for power10. Signed-off-by: Athira Rajeev --- Dependency: - On power10 PMU base enablement series V3: https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=190462 Changes from v3 -> v4 - Addressed review comments from Jordan and Michael Ellerman. This patch was initially part o

Re: [v3 12/15] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-07-24 Thread Athira Rajeev
ain random value which > will > allow user to pass this if condition unintentionally. > > Neat: PERF_REG_EXTENDED_MAX is a local variable so it should be in lowercase. > Any specific reason to define it in capital? Hi Ravi There is no specific reason. I will include both these changes in next version Thanks Athira Rajeev > > Ravi

[v3 01/15] powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers

2020-07-17 Thread Athira Rajeev
registers are added. Patch updates all relevant code that was using MMCR array ( cpuhw->mmcr[x]) to use newly introduced `struct`. This includes the PMU driver code for supported platforms (power5 to power9) and ISA macros for counter support functions. Signed-off-by: Athira Rajeev --- arch/powe

[v3 04/15] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-07-17 Thread Athira Rajeev
From: Madhavan Srinivasan PowerISA v3.1 includes new performance monitoring unit(PMU) special purpose registers (SPRs). They are Monitor Mode Control Register 3 (MMCR3) Sampled Instruction Event Register 2 (SIER2) Sampled Instruction Event Register 3 (SIER3) MMCR3 is added for further sampling

[v3 06/15] powerpc/xmon: Add PowerISA v3.1 PMU SPRs

2020-07-17 Thread Athira Rajeev
From: Madhavan Srinivasan PowerISA v3.1 added three new perfromance monitoring unit (PMU) speical purpose register (SPR). They are Monitor Mode Control Register 3 (MMCR3), Sampled Instruction Event Register 2 (SIER2), Sampled Instruction Event Register 3 (SIER3). Patch here adds a new dump

[v3 08/15] powerpc/perf: power10 Performance Monitoring support

2020-07-17 Thread Athira Rajeev
the support function in isa207_common.c to include power10 pmu hardware. [Enablement of base PMU driver code] Signed-off-by: Madhavan Srinivasan [Addition of ISA macros for counter support functions] Signed-off-by: Athira Rajeev [Fix compilation warning for missing prototype for init_power10_pmu

[v3 11/15] powerpc/perf: BHRB control to disable BHRB logic when not used

2020-07-17 Thread Athira Rajeev
ot enabled on request at runtime. Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 20 arch/powerpc/perf/isa207-common.c | 12 arch/powerpc/platforms/powernv/idle.c | 22 -- 3 files changed, 48 insertions(+), 6

[v3 13/15] tools/perf: Add perf tools support for extended register capability in powerpc

2020-07-17 Thread Athira Rajeev
extended mask at run time based on platform] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan --- tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++- tools/perf/arch/powerpc/include/perf_regs.h | 5 ++- tools/perf/arch/powerpc/util/header.c | 9 + tools

[v3 00/15] powerpc/perf: Add support for power10 PMU Hardware

2020-07-17 Thread Athira Rajeev
register capability in powerpc Athira Rajeev (10): powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR powerpc/perf: Update Power PMU cache_events to u64 type KVM: PPC: Book3S HV: Save/restore new PMU

[v3 09/15] powerpc/perf: Ignore the BHRB kernel address filtering for P10

2020-07-17 Thread Athira Rajeev
MSR[PR]=1 address to be written to BHRB buffer. Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 0ffb757d..bd125fe 100644 --- a/arch/powerpc

[v3 12/15] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-07-17 Thread Athira Rajeev
mmcr0 0x82008090 mmcr1 0x1e00 mmcr2 0x0 ... thread: perf:4784 Signed-off-by: Anju T Sudhakar [Defined PERF_REG_EXTENDED_MASK at run time to add support for different platforms ] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan --- arch/powerpc/include/asm

[v3 03/15] powerpc/perf: Update Power PMU cache_events to u64 type

2020-07-17 Thread Athira Rajeev
nts. Signed-off-by: Athira Rajeev --- arch/powerpc/include/asm/perf_event_server.h | 2 +- arch/powerpc/perf/core-book3s.c | 2 +- arch/powerpc/perf/generic-compat-pmu.c | 2 +- arch/powerpc/perf/mpc7450-pmu.c | 2 +- arch/powerpc/perf/power5+-pmu.c | 2 +- a

[v3 10/15] powerpc/perf: Add Power10 BHRB filter support for PERF_SAMPLE_BRANCH_IND_CALL/COND

2020-07-17 Thread Athira Rajeev
PowerISA v3.1 introduce filtering support for PERF_SAMPLE_BRANCH_IND_CALL/COND. The patch adds BHRB filter support for "ind_call" and "cond" in power10_bhrb_filter_map(). Signed-off-by: Athira Rajeev --- arch/powerpc/perf/power10-pmu.c | 13 +++-- 1 file changed,

[v3 14/15] powerpc/perf: Add extended regs support for power10 platform

2020-07-17 Thread Athira Rajeev
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10 and expose MMCR3, SIER2, SIER3 registers as part of extended regs. Also introduce `PERF_REG_PMU_MASK_31` to define extended mask value at runtime for power10 Signed-off-by: Athira Rajeev [Fix build failure on PPC32 platform

[v3 05/15] KVM: PPC: Book3S HV: Save/restore new PMU registers

2020-07-17 Thread Athira Rajeev
entering/exiting guest. Also includes changes to support KVM_REG_PPC_MMCR3/SIER2/SIER3. And adds new SPRs to KVM API documentation. Signed-off-by: Athira Rajeev --- Documentation/virt/kvm/api.rst| 3 +++ arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +- arch/powerpc/include/asm

[v3 15/15] tools/perf: Add perf tools support for extended regs in power10

2020-07-17 Thread Athira Rajeev
Added support for supported regs which are new in power10 ( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side to use with `-I?` option. Also added PVR check to send extended mask for power10 at kernel while capturing extended regs in each sample. Signed-off-by: Athira Rajeev --- tools

[v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR

2020-07-17 Thread Athira Rajeev
. Signed-off-by: Athira Rajeev --- arch/powerpc/include/asm/kvm_host.h | 4 +++- arch/powerpc/include/uapi/asm/kvm.h | 4 ++-- arch/powerpc/kernel/asm-offsets.c | 2 ++ arch/powerpc/kvm/book3s_hv.c | 16 ++-- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 12

[v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-17 Thread Athira Rajeev
From: Madhavan Srinivasan Add power10 feature function to dt_cpu_ftrs.c along with a power10 specific init() to initialize pmu sprs, sets the oprofile_cpu_type and cpu_features. This will enable performance monitoring unit(PMU) for Power10 in CPU features with "performance-monitor-power10". For

[PATCH V4 4/4] tools/perf: Add perf tools support for extended regs in power10

2020-07-26 Thread Athira Rajeev
Added support for supported regs which are new in power10 ( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side to use with `-I?` option. Also added PVR check to send extended mask for power10 at kernel while capturing extended regs in each sample. Signed-off-by: Athira Rajeev Reviewed

[PATCH V4 1/4] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-07-26 Thread Athira Rajeev
mmcr0 0x82008090 mmcr1 0x1e00 mmcr2 0x0 ... thread: perf:4784 Signed-off-by: Anju T Sudhakar [Defined PERF_REG_EXTENDED_MASK at run time to add support for different platforms ] Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan [Fix build issue using

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