[PATCH] spi_mpc8xxx: fix writing to adress 0

2010-09-16 Thread christophe leroy
This patch applies to 2.6.34.7 (already included in 2.6.35.4) It fixes an issue when sending only or receiving only (mspi-tx-dma was reset as when no tx_buf is defined, tx_dma is 0) Signed-off-by: christophe leroy christophe.le...@c-s.fr diff -urN a/drivers/spi/spi_mpc8xxx.c b/drivers/spi

[PATCH] spi_mpc8xxx: issue with using definition of pram in Device Tree

2010-09-16 Thread christophe leroy
This patch applies to 2.6.34.7 and 2.6.35.4 It fixes an issue during the probe for CPM1 with definition of parameter ram from DTS Signed-off-by: christophe leroy christophe.le...@c-s.fr diff -urN b/drivers/spi/spi_mpc8xxx.c c/drivers/spi/spi_mpc8xxx.c --- b/drivers/spi/spi_mpc8xxx.c 2010-09-08

[PATCH] spi_mpc8xxx: fix buffer overrun when sending only/receiving only more than PAGE_SIZE bytes

2010-09-16 Thread christophe leroy
This patch applies to 2.6.34.7 and 2.6.35.4 It fixes an issue when sending only or receiving only more than PAGE_SIZE bytes Signed-off-by: christophe leroy christophe.le...@c-s.fr diff -urN c/drivers/spi/spi_mpc8xxx.c d/drivers/spi/spi_mpc8xxx.c --- c/drivers/spi/spi_mpc8xxx.c 2010-09-08 16:44

[PATCH v3] Enhanced support for MPC8xx/8xxx watchdog

2013-08-08 Thread Christophe Leroy
the userspace timeout. This patch also adds the WDIOC_SETTIMEOUT ioctl to the driver. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- linux-3.8.13/drivers/watchdog/mpc8xxx_wdt.c 2013-05-11 22:57:46.0 +0200 +++ linux/drivers/watchdog/mpc8xxx_wdt.c2013-08-08 02:12:15.0

[PATCH] Adding proper request of GPIO used by cpm_uart driver

2013-08-21 Thread Christophe Leroy
cpm_uart serial driver uses GPIO for control signals. In order to be used properly, GPIOs have to be reserved. Comment in gpiolib.c considers illegal the use of GPIOs without requesting them. In addition, the direction of the GPIO has to be set properly. Signed-off-by: Christophe Leroy

[PATCH] powerpc/mpc8xx: Clearer Oops message for Software Emulation Exception

2013-08-28 Thread Christophe Leroy
. The new message tries to be more generic in order to make the user understand that the Oops is due to something wrong with an instruction, not necessarily due to an FPU instruction. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr diff -ur linux-3.11-rc6/arch/powerpc/kernel/traps.c linux

[PATCH] powerpc 8xx: Reverting commit e0908085fc2391c85b85fb814ae1df377c8e0dcb which has become useless

2013-09-11 Thread Christophe Leroy
on the 8xx. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr diff -ur linux-3.11.org/arch/powerpc/mm/pgtable.c linux-3.11/arch/powerpc/mm/pgtable.c --- linux-3.11.org/arch/powerpc/mm/pgtable.c2013-09-02 22:46:10.0 +0200 +++ linux-3.11/arch/powerpc/mm/pgtable.c2013-09-09 11

[PATCH] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB

2013-09-11 Thread Christophe Leroy
Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three 8Mbytes pages. But the setting of the MD_CTR was missing so as the index is decremented every DTLB update, the pinning of the third 8Mbytes page was overwriting the DTLB entry for IMMR. Signed-off-by: Christophe Leroy

[PATCH] powerpc 8xx: Reverting commit e0908085fc2391c85b85fb814ae1df377c8e0dcb which has become useless

2013-09-11 Thread Christophe Leroy
on the 8xx. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr diff -ur linux-3.11.org/arch/powerpc/mm/pgtable.c linux-3.11/arch/powerpc/mm/pgtable.c --- linux-3.11.org/arch/powerpc/mm/pgtable.c2013-09-02 22:46:10.0 +0200 +++ linux-3.11/arch/powerpc/mm/pgtable.c2013-09-09 11

[PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB

2013-09-12 Thread Christophe Leroy
This is a reorganisation of the setup of the TLB at kernel startup, in order to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866 and MPC885 reference manuals. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S

[PATCH v3] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB

2013-09-17 Thread Christophe Leroy
written being entry 31, next entries would possibly get overwritten after. We are now starting from entry 31 and decrementing. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S linux-3.11/arch/powerpc/kernel/head_8xx.S --- linux-3.11.org

[PATCH v4] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB

2013-09-24 Thread Christophe Leroy
was not pinned. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S linux-3.11/arch/powerpc/kernel/head_8xx.S --- linux-3.11.org/arch/powerpc/kernel/head_8xx.S 2013-09-02 22:46:10.0 +0200 +++ linux-3.11/arch/powerpc/kernel

[PATCH] Powerpc 8xx CPM_UART delay in receive

2012-08-14 Thread Christophe Leroy
bauds. This fix limits to one byte the waiting period. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- linux-3.5-vanilla/drivers/tty/serial/cpm_uart/cpm_uart_core.c 2012-07-21 22:58:29.0 +0200 +++ linux-3.5/drivers/tty/serial/cpm_uart/cpm_uart_core.c 2012-08-09 17

[PATCH] Powerpc 8xx CPM_UART desynchronisation

2012-08-14 Thread Christophe Leroy
Hello, I'm not sure who to address this Patch to. It fixes a desynchronisation problem with CPM UART driver on Powerpc MPC8xx. The problem happens if data is received before the device is open by the user application. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- linux-3.5

[PATCH 00/20] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

2014-08-08 Thread Christophe Leroy
This patchset: * provides several MMU TLB handling optimisation on MPC8xx. * adds support of 16k pages on MPC8xx. All changes have been successfully tested on a custom board equipped with MPC885 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Tested-by: Christophe Leroy christophe.le...@c

[PATCH 03/20] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

2014-08-08 Thread Christophe Leroy
Exception InstructionAccess does not exist on MPC8xx. No need to branch there from somewhere else. Handling can be done directly in InstructionTLBError Exception. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 17 +++-- 1 files

[PATCH 04/20] powerpc/8xx: Remove loading of r10 at end of FixupDAR

2014-08-08 Thread Christophe Leroy
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore after FixupDAR. There is therefore no need to set it up with the value of DAR. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |7 +++ 1 files changed, 3 insertions

[PATCH 02/20] powerpc/8xx: Use SCRATCH0 and SCRATCH1 also for TLB handlers

2014-08-08 Thread Christophe Leroy
-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 104 -- 1 files changed, 36 insertions(+), 68 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 1329c5a..3af6db1 100644 --- a/arch

[PATCH 07/20] powerpc/8xx: DataAccess exception not generated by MPC8xx

2014-08-08 Thread Christophe Leroy
DataAccess exception is never generated by MPC8xx so do the job directly where it is used to avoid an unnecessary branching. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 23 ++- 1 files changed, 10 insertions(+), 13 deletions

[PATCH 01/20] powerpc/8xx: Declare SPRG2 as a SCRATCH register

2014-08-08 Thread Christophe Leroy
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a scratch register just like SPRG0 and SPRG1. So Declare it as such and fix the comment which is not valid anymore since that commit. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm

[PATCH 08/20] powerpc/8xx: No need to restore registers and save them again.

2014-08-08 Thread Christophe Leroy
In DTLBError handler there is not need to restore r10, r11 and cr registers after fixing DAR as they are saved again to the same place just after. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |4 ++-- 1 files changed, 2 insertions(+), 2

[PATCH 05/20] powerpc/8xx: Fix comment about DIRTY update

2014-08-08 Thread Christophe Leroy
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not handled here anymore. So we fix the comment. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |8 ++-- 1 files changed, 2 insertions(+), 6 deletions(-) diff --git

[PATCH 09/20] powerpc/8xx: Optimize verification in FixupDAR

2014-08-08 Thread Christophe Leroy
By XORing the upper part of the instruction code, we get a value that can directly be verified with the second test and we can remove the first test. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |6 ++ 1 files changed, 2 insertions(+), 4

[PATCH 11/20] powerpc/8xx: Align swapper_pg_dir on 16 bits boundary

2014-08-08 Thread Christophe Leroy
Lets save one cycle by aligning swapper_pg_dir on 16 bits boundary. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 13 + 1 files changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc

[PATCH 06/20] powerpc/8xx: No need to save r10 and r3 when not calling FixupDAR

2014-08-08 Thread Christophe Leroy
r10 and r3 are only used inside FixupDAR function. So lets save them inside that function only. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 27 +-- 1 files changed, 13 insertions(+), 14 deletions(-) diff --git a/arch

[PATCH 12/20] powerpc/8xx: Use M_TW instead of M_TWB

2014-08-08 Thread Christophe Leroy
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires 4k aligned tables, which is only the case with 4k pages. Consequently, we have to calculate the level 1 table index by ourselves. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel

[PATCH 10/20] powerpc/8xx: Duplicate two insns instead of branching

2014-08-08 Thread Christophe Leroy
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions and avoid the branching. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel

[PATCH 14/20] powerpc/8xx: Use PAGE size related consts

2014-08-08 Thread Christophe Leroy
For PAGE size related operations, use PAGE size consts in order to be able to use different page size in the futur. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 29 ++--- 1 files changed, 18 insertions(+), 11 deletions

[PATCH 13/20] powerpc/8xx: Don't use MD_TWC for walk

2014-08-08 Thread Christophe Leroy
MD_TWC can only be used properly with 4k pages. So lets calculate level 2 table index by ourselves. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 30 +- 1 files changed, 13 insertions(+), 17 deletions(-) diff --git

[PATCH 20/20] powerpc/8xx: Don't restore regs to save them again.

2014-08-08 Thread Christophe Leroy
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss handler as they are saved again to the same place in ITLBError handler we are jumping to. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |8 +--- 1 files changed, 5

[PATCH 17/20] powerpc/8xx: Better readibility of ERRATA CPU6 handling

2014-08-08 Thread Christophe Leroy
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro. Then we don't have to worry about this address directly in the code. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 29 - 1 files changed

[PATCH 18/20] powerpc/8xx: set PTE bit 22 off TLBmiss

2014-08-08 Thread Christophe Leroy
No need to re-set this bit at each TLB miss. Let's set it in the PTE. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm/pgtable-ppc32.h | 21 + arch/powerpc/include/asm/pte-8xx.h |7 +-- arch/powerpc/kernel/head_8xx.S

[PATCH 19/20] powerpc/8xx: _PMD_PRESENT already set in level 1 entries

2014-08-08 Thread Christophe Leroy
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit during TLB loading is useless. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel

[PATCH 15/20] powerpc/8xx: Const for TLB RPN forced value

2014-08-08 Thread Christophe Leroy
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked to the page size and will vary when we change the page size. Lets define a const for it in order to have it at only one place. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S

[PATCH 16/20] powerpc/8xx: Implement 16k pages

2014-08-08 Thread Christophe Leroy
This patch activates the handling of 16k pages on the MPC8xx. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/Kconfig |2 +- arch/powerpc/include/asm/mmu-8xx.h |2 ++ arch/powerpc/kernel/head_8xx.S |4 3 files changed, 7 insertions

[PATCH v2 00/19] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

2014-08-29 Thread Christophe Leroy
was implementing a 16 bit alignment of the PGDIR. It is not worth potentially wasting up to 64k of memory just for removing one instruction (ori). 2) I managed to preserve r11 while calculating the level 2 address, therefore no more need to save r11 into CR. Signed-off-by: Christophe Leroy

[PATCH v2 01/19] powerpc/8xx: Declare SPRG2 as a SCRATCH register

2014-08-29 Thread Christophe Leroy
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a scratch register just like SPRG0 and SPRG1. So Declare it as such and fix the comment which is not valid anymore since that commit. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm

[PATCH v2 02/19] powerpc/8xx: Use SCRATCH0 and SCRATCH1 also for TLB handlers

2014-08-29 Thread Christophe Leroy
-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 104 -- 1 files changed, 36 insertions(+), 68 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 1329c5a..3af6db1 100644 --- a/arch

[PATCH v2 03/19] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

2014-08-29 Thread Christophe Leroy
Exception InstructionAccess does not exist on MPC8xx. No need to branch there from somewhere else. Handling can be done directly in InstructionTLBError Exception. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 17 +++-- 1 files

[PATCH v2 05/19] powerpc/8xx: Fix comment about DIRTY update

2014-08-29 Thread Christophe Leroy
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not handled here anymore. So we fix the comment. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |8 ++-- 1 files changed, 2 insertions(+), 6 deletions(-) diff --git

[PATCH v2 04/19] powerpc/8xx: Remove loading of r10 at end of FixupDAR

2014-08-29 Thread Christophe Leroy
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore after FixupDAR. There is therefore no need to set it up with the value of DAR. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |7 +++ 1 files changed, 3 insertions

[PATCH v2 10/19] powerpc/8xx: Duplicate two insns instead of branching

2014-08-29 Thread Christophe Leroy
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions and avoid the branching. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel

[PATCH v2 06/19] powerpc/8xx: No need to save r10 and r3 when not calling FixupDAR

2014-08-29 Thread Christophe Leroy
r10 and r3 are only used inside FixupDAR function. So lets save them inside that function only. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 27 +-- 1 files changed, 13 insertions(+), 14 deletions(-) diff --git a/arch

[PATCH v2 15/19] powerpc/8xx: Implement 16k pages

2014-08-29 Thread Christophe Leroy
This patch activates the handling of 16k pages on the MPC8xx. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/Kconfig |2 +- arch/powerpc/include/asm/mmu-8xx.h |2 ++ arch/powerpc/kernel/head_8xx.S |4 3 files changed, 7 insertions

[PATCH v2 18/19] powerpc/8xx: _PMD_PRESENT already set in level 1 entries

2014-08-29 Thread Christophe Leroy
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit during TLB loading is useless. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel

[PATCH v2 09/19] powerpc/8xx: Optimize verification in FixupDAR

2014-08-29 Thread Christophe Leroy
By XORing the upper part of the instruction code, we get a value that can directly be verified with the second test and we can remove the first test. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |6 ++ 1 files changed, 2 insertions(+), 4

[PATCH v2 19/19] powerpc/8xx: Don't restore regs to save them again.

2014-08-29 Thread Christophe Leroy
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss handler as they are saved again to the same place in ITLBError handler we are jumping to. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |8 +--- 1 files changed, 5

[PATCH v2 17/19] powerpc/8xx: set PTE bit 22 off TLBmiss

2014-08-29 Thread Christophe Leroy
No need to re-set this bit at each TLB miss. Let's set it in the PTE. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm/pgtable-ppc32.h | 21 + arch/powerpc/include/asm/pte-8xx.h |7 +-- arch/powerpc/kernel/head_8xx.S

[PATCH v2 12/19] powerpc/8xx: Don't use MD_TWC for walk

2014-08-29 Thread Christophe Leroy
MD_TWC can only be used properly with 4k pages. So lets calculate level 2 table index by ourselves. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 28 1 files changed, 12 insertions(+), 16 deletions(-) diff --git

[PATCH v2 08/19] powerpc/8xx: No need to restore registers and save them again.

2014-08-29 Thread Christophe Leroy
In DTLBError handler there is not need to restore r10, r11 and cr registers after fixing DAR as they are saved again to the same place just after. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S |4 ++-- 1 files changed, 2 insertions(+), 2

[PATCH v2 07/19] powerpc/8xx: DataAccess exception not generated by MPC8xx

2014-08-29 Thread Christophe Leroy
DataAccess exception is never generated by MPC8xx so do the job directly where it is used to avoid an unnecessary branching. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 23 ++- 1 files changed, 10 insertions(+), 13 deletions

[PATCH v2 13/19] powerpc/8xx: Use PAGE size related consts

2014-08-29 Thread Christophe Leroy
For PAGE size related operations, use PAGE size consts in order to be able to use different page size in the futur. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 30 ++ 1 files changed, 18 insertions(+), 12 deletions

[PATCH v2 14/19] powerpc/8xx: Const for TLB RPN forced value

2014-08-29 Thread Christophe Leroy
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked to the page size and will vary when we change the page size. Lets define a const for it in order to have it at only one place. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S

[PATCH v2 11/19] powerpc/8xx: Use M_TW instead of M_TWB

2014-08-29 Thread Christophe Leroy
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires 4k aligned tables, which is only the case with 4k pages. Consequently, we have to calculate the level 1 table index by ourselves. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel

[PATCH v2 16/19] powerpc/8xx: Better readibility of ERRATA CPU6 handling

2014-08-29 Thread Christophe Leroy
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro. Then we don't have to worry about this address directly in the code. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 29 - 1 files changed

[PATCH v3 01/21] powerpc/8xx: Declare SPRG2 as a SCRATCH register

2014-09-17 Thread Christophe Leroy
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a scratch register just like SPRG0 and SPRG1. So Declare it as such and fix the comment which is not valid anymore since that commit. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes

[PATCH v3 03/21] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

2014-09-17 Thread Christophe Leroy
Exception InstructionAccess does not exist on MPC8xx. No need to branch there from somewhere else. Handling can be done directly in InstructionTLBError Exception. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - arch/powerpc/mm/fault.c uses

[PATCH v3 02/21] powerpc/8xx: Use SCRATCH0 and SCRATCH1 also for TLB handlers

2014-09-17 Thread Christophe Leroy
-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S | 104 -- 1 files changed, 36 insertions(+), 68 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel

[PATCH v3 04/21] powerpc/8xx: Remove loading of r10 at end of FixupDAR

2014-09-17 Thread Christophe Leroy
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore after FixupDAR. There is therefore no need to set it up with the value of DAR. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S

[PATCH v3 00/21] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

2014-09-17 Thread Christophe Leroy
This patchset: 1) provides several MMU TLB handling optimisation on MPC8xx. 2) adds support of 16k pages on MPC8xx. All changes have been successfully tested on a custom board equipped with MPC885 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Tested-by: Christophe Leroy christophe.le

[PATCH v3 05/21] powerpc/8xx: Fix comment about DIRTY update

2014-09-17 Thread Christophe Leroy
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not handled here anymore. So we fix the comment. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S |8 ++-- 1 files changed, 2

[PATCH v3 09/21] powerpc/8xx: Optimize verification in FixupDAR

2014-09-17 Thread Christophe Leroy
By XORing the upper part of the instruction code, we get a value that can directly be verified with the second test and we can remove the first test. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S |6

[PATCH v3 07/21] powerpc/8xx: DataAccess exception not generated by MPC8xx

2014-09-17 Thread Christophe Leroy
DataAccess exception is never generated by MPC8xx so do the job directly where it is used to avoid an unnecessary branching. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - arch/powerpc/mm/fault.c uses the vector number, so make sure

[PATCH v3 12/21] powerpc/8xx: Don't use MD_TWC for walk

2014-09-17 Thread Christophe Leroy
MD_TWC can only be used properly with 4k pages. So lets calculate level 2 table index by ourselves. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - No need to save r11 in cr, we can do without modifying r11 in DataStoreTLBMiss Changes in v3: - None arch/powerpc

[PATCH v3 13/21] powerpc/8xx: Use PAGE size related consts

2014-09-17 Thread Christophe Leroy
For PAGE size related operations, use PAGE size consts in order to be able to use different page size in the futur. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S | 30 ++ 1

[PATCH v3 10/21] powerpc/8xx: Duplicate two insns instead of branching

2014-09-17 Thread Christophe Leroy
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions and avoid the branching. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S |6 -- 1 files changed, 4 insertions(+), 2

[PATCH v3 14/21] powerpc/8xx: Const for TLB RPN forced value

2014-09-17 Thread Christophe Leroy
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked to the page size and will vary when we change the page size. Lets define a const for it in order to have it at only one place. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes

[PATCH v3 08/21] powerpc/8xx: No need to restore registers and save them again.

2014-09-17 Thread Christophe Leroy
In DTLBError handler there is not need to restore r10, r11 and cr registers after fixing DAR as they are saved again to the same place just after. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S |4

[PATCH v3 11/21] powerpc/8xx: Use M_TW instead of M_TWB

2014-09-17 Thread Christophe Leroy
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires 4k aligned tables, which is only the case with 4k pages. Consequently, we have to calculate the level 1 table index by ourselves. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None

[PATCH v3 06/21] powerpc/8xx: No need to save r10 and r3 when not calling FixupDAR

2014-09-17 Thread Christophe Leroy
r10 and r3 are only used inside FixupDAR function. So lets save them inside that function only. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S | 27 +-- 1 files changed, 13

[PATCH v3 15/21] powerpc/8xx: Implement 16k pages

2014-09-17 Thread Christophe Leroy
This patch activates the handling of 16k pages on the MPC8xx. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/Kconfig |2 +- arch/powerpc/include/asm/mmu-8xx.h |2 ++ arch/powerpc/kernel/head_8xx.S

[PATCH v3 17/21] powerpc/8xx: set PTE bit 22 off TLBmiss

2014-09-17 Thread Christophe Leroy
No need to re-set this bit at each TLB miss. Let's set it in the PTE. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - Removed PPC405 related macro from PPC8xx specific code - PTE_NONE_MASK doesn't need PAGE_ACCESSED in Linux 2.6 arch/powerpc

[PATCH v3 19/21] powerpc/8xx: Don't restore regs to save them again.

2014-09-17 Thread Christophe Leroy
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss handler as they are saved again to the same place in ITLBError handler we are jumping to. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel

[PATCH v3 18/21] powerpc/8xx: _PMD_PRESENT already set in level 1 entries

2014-09-17 Thread Christophe Leroy
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit during TLB loading is useless. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S |2 -- 1 files changed, 0 insertions(+), 2

[PATCH v3 21/21] powerpc/8xx: Invalidate non present TLB as early as possible

2014-09-17 Thread Christophe Leroy
the TLB as soon as possible. This also has the advantage of removing some 8xx specific code from fault.c Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v3: - New linux/arch/powerpc/kernel/head_8xx.S | 15 ++- linux/arch/powerpc/mm/fault.c| 7 --- 2

[PATCH v3 16/21] powerpc/8xx: Better readibility of ERRATA CPU6 handling

2014-09-17 Thread Christophe Leroy
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro. Then we don't have to worry about this address directly in the code. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None arch/powerpc/kernel/head_8xx.S | 29

[PATCH v3 20/21] powerpc/8xx: Use DAR to save r3 for CPU6 ERRATA

2014-09-17 Thread Christophe Leroy
As we are not using anymore DAR to save registers, it is now available for saving the r3 register used for CPU6 ERRATA handling. Therefore we can remove the major hack which was to use memory location 0 to save r3. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v3: - New

Re: [PATCH v3 00/21] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

2014-09-17 Thread christophe leroy
Le 17/09/2014 18:40, Scott Wood a écrit : On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote: This patchset: 1) provides several MMU TLB handling optimisation on MPC8xx. 2) adds support of 16k pages on MPC8xx. All changes have been successfully tested on a custom board equipped

Re: [PATCH v3 03/21] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

2014-09-18 Thread christophe leroy
Le 18/09/2014 18:42, leroy christophe a écrit : Le 18/09/2014 17:15, Joakim Tjernlund a écrit : Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17 18:36:57: Exception InstructionAccess does not exist on MPC8xx. No need to branch there from somewhere else. Handling can be done

Re: [PATCH v3 03/21] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

2014-09-18 Thread christophe leroy
Le 18/09/2014 20:12, Joakim Tjernlund a écrit : leroy christophe christophe.le...@c-s.fr wrote on 2014/09/18 18:42:14: Le 18/09/2014 17:15, Joakim Tjernlund a écrit : Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17 18:36:57: Exception InstructionAccess does not exist on MPC8xx

[PATCH v4 02/21] powerpc/8xx: Use SCRATCH0 and SCRATCH1 also for TLB handlers

2014-09-19 Thread Christophe Leroy
-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/powerpc/kernel/head_8xx.S | 104 -- 1 files changed, 36 insertions(+), 68 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch

[PATCH v4 00/21] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

2014-09-19 Thread Christophe Leroy
This patchset: 1) provides several MMU TLB handling optimisation on MPC8xx. 2) adds support of 16k pages on MPC8xx. All changes have been successfully tested on a custom board equipped with MPC885 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Tested-by: Christophe Leroy christophe.le

[PATCH v4 01/21] powerpc/8xx: Declare SPRG2 as a SCRATCH register

2014-09-19 Thread Christophe Leroy
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a scratch register just like SPRG0 and SPRG1. So Declare it as such and fix the comment which is not valid anymore since that commit. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes

[PATCH v4 03/21] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

2014-09-19 Thread Christophe Leroy
Exception InstructionAccess does not exist on MPC8xx. No need to branch there from somewhere else. Handling can be done directly in InstructionTLBError Exception. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - arch/powerpc/mm/fault.c uses

[PATCH v4 04/21] powerpc/8xx: Remove loading of r10 at end of FixupDAR

2014-09-19 Thread Christophe Leroy
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore after FixupDAR. There is therefore no need to set it up with the value of DAR. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch

[PATCH v4 10/21] powerpc/8xx: Duplicate two insns instead of branching

2014-09-19 Thread Christophe Leroy
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions and avoid the branching. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/powerpc/kernel/head_8xx.S |6 -- 1 files changed, 4

[PATCH v4 05/21] powerpc/8xx: Fix comment about DIRTY update

2014-09-19 Thread Christophe Leroy
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not handled here anymore. So we fix the comment. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/powerpc/kernel/head_8xx.S | 8

[PATCH v4 07/21] powerpc/8xx: DataAccess exception not generated by MPC8xx

2014-09-19 Thread Christophe Leroy
DataAccess exception is never generated by MPC8xx so do the job directly where it is used to avoid an unnecessary branching. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - arch/powerpc/mm/fault.c uses the vector number, so make sure

[PATCH v4 12/21] powerpc/8xx: Don't use MD_TWC for walk

2014-09-19 Thread Christophe Leroy
MD_TWC can only be used properly with 4k pages. So lets calculate level 2 table index by ourselves. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - No need to save r11 in cr, we can do without modifying r11 in DataStoreTLBMiss Changes in v3: - None Changes in v4

[PATCH v4 14/21] powerpc/8xx: Const for TLB RPN forced value

2014-09-19 Thread Christophe Leroy
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked to the page size and will vary when we change the page size. Lets define a const for it in order to have it at only one place. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes

[PATCH v4 19/21] powerpc/8xx: Don't restore regs to save them again.

2014-09-19 Thread Christophe Leroy
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss handler as they are saved again to the same place in ITLBError handler we are jumping to. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None

[PATCH v4 21/21] powerpc/8xx: Invalidate non present TLB as early as possible

2014-09-19 Thread Christophe Leroy
the TLB as soon as possible. This also has the advantage of removing some 8xx specific code from fault.c Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v3: - New Changes in v4: - None (but impacted by changes in patch 3 and 7) arch/powerpc/kernel/head_8xx.S | 15

[PATCH v4 16/21] powerpc/8xx: Better readibility of ERRATA CPU6 handling

2014-09-19 Thread Christophe Leroy
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro. Then we don't have to worry about this address directly in the code. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/powerpc

[PATCH v4 18/21] powerpc/8xx: _PMD_PRESENT already set in level 1 entries

2014-09-19 Thread Christophe Leroy
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit during TLB loading is useless. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/powerpc/kernel/head_8xx.S |2 -- 1 files changed

[PATCH v4 17/21] powerpc/8xx: set PTE bit 22 off TLBmiss

2014-09-19 Thread Christophe Leroy
No need to re-set this bit at each TLB miss. Let's set it in the PTE. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - Removed PPC405 related macro from PPC8xx specific code - PTE_NONE_MASK doesn't need PAGE_ACCESSED in Linux 2.6 Changes in v4

[PATCH v4 20/21] powerpc/8xx: Use DAR to save r3 for CPU6 ERRATA

2014-09-19 Thread Christophe Leroy
As we are not using anymore DAR to save registers, it is now available for saving the r3 register used for CPU6 ERRATA handling. Therefore we can remove the major hack which was to use memory location 0 to save r3. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v3: - New

[PATCH v4 15/21] powerpc/8xx: Implement 16k pages

2014-09-19 Thread Christophe Leroy
This patch activates the handling of 16k pages on the MPC8xx. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/powerpc/Kconfig |2 +- arch/powerpc/include/asm/mmu-8xx.h |2 ++ arch/powerpc

[PATCH v4 11/21] powerpc/8xx: Use M_TW instead of M_TWB

2014-09-19 Thread Christophe Leroy
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires 4k aligned tables, which is only the case with 4k pages. Consequently, we have to calculate the level 1 table index by ourselves. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None

[PATCH v4 09/21] powerpc/8xx: Optimize verification in FixupDAR

2014-09-19 Thread Christophe Leroy
By XORing the upper part of the instruction code, we get a value that can directly be verified with the second test and we can remove the first test. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/powerpc

[PATCH v4 06/21] powerpc/8xx: No need to save r10 and r3 when not calling FixupDAR

2014-09-19 Thread Christophe Leroy
r10 and r3 are only used inside FixupDAR function. So lets save them inside that function only. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/powerpc/kernel/head_8xx.S | 27 +-- 1

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