Hi,
Just to be on the same page, are you using the Freescale Embedded
Hypervisor provided with the Freescale SDK or other embedded hypervisor?
Anyway, the question is not much related with the Linux kernel, so you
should probably redirect your question to Freescale support. You can
reach
From: Diana Craciun diana.crac...@freescale.com
On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor
state can execute TLB management instructions. If EPCR[DGTMI]=0
tlbwe and tlbilx are allowed to execute normally in the guest state.
A hypervisor may choose to virtualize TLB1
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral
From: Diana Craciun diana.crac...@freescale.com
Updated the compatible to reflect that CCF hardware
is different on T4240
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/b4860emu.dts | 2 +-
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4
arch
On 04/19/2014 01:07 AM, Scott Wood wrote:
On Fri, 2014-04-18 at 18:21 +0300, Diana Craciun wrote:
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch
On 04/19/2014 12:33 AM, Scott Wood wrote:
On Fri, 2014-04-18 at 18:11 +0300, Diana Craciun wrote:
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/b4860emu.dts | 7 ++-
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 2 +-
arch
On 05/06/2014 07:57 PM, Scott Wood wrote:
On Tue, 2014-05-06 at 17:56 +0300, Diana Craciun wrote:
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
v2:
Added missing p5040
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl
On 06/06/2014 10:18 AM, Shengzhou Liu wrote:
The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
Architecture processor cores with high-performance datapath acceleration
logic and network and peripheral bus interfaces required for networking,
telecom/datacom, wireless
From: Diana Craciun diana.crac...@freescale.com
On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor
state can execute TLB management instructions. If EPCR[DGTMI]=0
tlbwe and tlbilx are allowed to execute normally in the guest state.
A hypervisor may choose to virtualize TLB1
On 02/15/2013 02:11 AM, Benjamin Herrenschmidt wrote:
On Thu, 2013-02-14 at 14:56 +0200, Diana Craciun wrote:
From: Diana Craciun diana.crac...@freescale.com
On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor
state can execute TLB management instructions. If EPCR[DGTMI]=0
On 02/18/2013 02:52 PM, Varun Sethi wrote:
+
+#define PAACE_TCEF_FORMAT0_8B 0x00
+#define PAACE_TCEF_FORMAT1_RSVD 0x01
+
+#define PAACE_NUMBER_ENTRIES0x1FF
Where is this number coming from?
Diana
___
Linuxppc-dev mailing list
On 02/18/2013 02:52 PM, Varun Sethi wrote:
+/**
+ * pamu_get_ppaace() - Return the primary PACCE
+ * @liodn: liodn PAACT index for desired PAACE
+ *
+ * Returns the ppace pointer upon success else return
+ * null.
+ */
+static struct paace *pamu_get_ppaace(int liodn)
+{
+ if (!ppaact ||
On 02/19/2013 09:47 PM, Scott Wood wrote:
On 02/15/2013 09:16:15 AM, Diana Craciun wrote:
On 02/15/2013 02:11 AM, Benjamin Herrenschmidt wrote:
On Thu, 2013-02-14 at 14:56 +0200, Diana Craciun wrote:
From: Diana Craciun diana.crac...@freescale.com
On Freescale e6500 cores EPCR[DGTMI
On 02/20/2013 04:22 PM, Stuart Yoder wrote:
On Tue, Feb 19, 2013 at 1:47 PM, Scott Wood scottw...@freescale.com wrote:
This patch addresses boot-time invalidations only. How will you handle
hugetlb invalidations (or indirect entry invalidations, once that becomes
supported)?
We do envision
From: Diana CRACIUN diana.crac...@freescale.com
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:
e.g. reg = 0x41600 0x200 0x44140 4;
The first region contains the address and length of the MSI
register set
Please ignore this, I put a wrong subject.
Thanks,
Diana
On 02/01/2012 05:40 PM, Diana Craciun wrote:
From: Diana CRACIUNdiana.crac...@freescale.com
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:
e.g
From: Diana CRACIUN diana.crac...@freescale.com
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:
e.g. reg = 0x41600 0x200 0x44140 4;
The first region contains the address and length of the MSI
register set
From: Diana CRACIUN diana.crac...@freescale.com
The association in the decice tree between PCI and MSI
using fsl,msi property was an artificial one and it does
not reflect the actual hardware.
Signed-off-by: Diana CRACIUN diana.crac...@freescale.com
---
arch/powerpc/boot/dts/p2041rdb.dts |3
for the property:
fsl,needs-spec-barrier-for-bounds-check
Signed-off-by: Diana Craciun <diana.crac...@nxp.com>
---
The patches were created on top of the BOOK3S 64 patches:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2018-April/172137.html
arch/powerpc/include/asm/barrier.h
Used barrier_nospec to sanitize the syscall table.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/entry_32.S | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index eb8d01b..e3ff9ace 100644
--- a/arch/powerpc
The speculation barrier can be disabled from the command line
with the parameter: "nospectre_v1".
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/security.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powe
Implement barrier_nospec for NXP PowerPC Book3E processors.
Diana Craciun (3):
Disable the speculation barrier from the command line
Add barrier_nospec implementation for NXP PowerPC Book3E
Implement cpu_show_spectre_v1/v2 for NXP PowerPC Book3E
arch/powerpc/Kconfig | 2
Implement the barrier_nospec as a isync;sync instruction sequence.
The implementation uses the infrastructure built for BOOK3S 64.
Signed-off-by: Diana Craciun
---
arch/powerpc/include/asm/barrier.h | 10 ++
arch/powerpc/include/asm/setup.h | 2 +-
arch/powerpc/kernel/Makefile
Signed-off-by: Diana Craciun
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/kernel/security.c | 15 +++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 940c955..a781d60 100644
--- a/arch/powerpc/Kconfig
+++ b
Implement the barrier_nospec as a isync;sync instruction sequence.
The implementation uses the infrastructure built for BOOK3S 64.
Signed-off-by: Diana Craciun
---
History:
v3-->v4
- fixed compilation issues
v2-->v3
- added PPC_NOSPEC Kconfig
- addressed the review co
Used barrier_nospec to sanitize the syscall table.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- included in the series
arch/powerpc/kernel/entry_32.S | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
in
The speculation barrier can be disabled from the command line
with the parameter: "nospectre_v1".
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- no changes
arch/powerpc/kernel/security.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/p
Implement barrier_nospec for NXP PowerPC Book3E processors.
Diana Craciun (6):
Disable the speculation barrier from the command line
Document nospectre_v1 kernel parameter.
Make stf barrier PPC_BOOK3S_64 specific.
Enable cpu vulnerabilities reporting for NXP PPC BOOK3E
Add
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- new
Documentation/admin-guide/kernel-parameters.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/admin-guide/kernel-parameters.txt
b/Documentation/admin-guide/kernel-parameters.txt
index efc7aa7..b346cc7 100
The NXP PPC Book3E platforms are not vulnerable to meltdown and
Spectre v4, so make them PPC_BOOK3S_64 specific.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- used the existing functions for spectre v1/v2
arch/powerpc/Kconfig | 7 ++-
arch/powerpc/kernel/security.c
NXP Book3E platforms are not vulnerable to speculative store
bypass, so make the mitigations PPC_BOOK3S_64 specific.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- new
arch/powerpc/kernel/security.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/kernel/security.
The speculation barrier can be disabled from the command line
with the parameter: "nospectre_v1".
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- no changes
arch/powerpc/kernel/security.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/p
Implement barrier_nospec for NXP PowerPC Book3E processors.
Diana Craciun (6):
Disable the speculation barrier from the command line
Document nospectre_v1 kernel parameter.
Make stf barrier PPC_BOOK3S_64 specific.
Enable cpu vulnerabilities reporting for NXP PPC BOOK3E
Add
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- new
Documentation/admin-guide/kernel-parameters.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/admin-guide/kernel-parameters.txt
b/Documentation/admin-guide/kernel-parameters.txt
index efc7aa7..b346cc7 100
NXP Book3E platforms are not vulnerable to speculative store
bypass, so make the mitigations PPC_BOOK3S_64 specific.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- new
arch/powerpc/kernel/security.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/kernel/security.
The NXP PPC Book3E platforms are not vulnerable to meltdown, so make it
PPC_BOOK3S_64 specific.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- used the existing functions for spectre v1/v2
arch/powerpc/Kconfig | 7 ++-
arch/powerpc/kernel/security.c | 2 ++
2 files chan
Implement the barrier_nospec as a isync;sync instruction sequence.
The implementation uses the infrastructure built for BOOK3S 64.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- added PPC_NOSPEC Kconfig
- addressed the review comments
It was a discussion at the previous review cycle ab
Used barrier_nospec to sanitize the syscall table.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- included in the series
arch/powerpc/kernel/entry_32.S | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
in
The BUCSR register can be used to invalidate the entries in the
branch prediction mechanisms.
Signed-off-by: Diana Craciun
---
arch/powerpc/include/asm/ppc_asm.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc_asm.h
b/arch/powerpc/include/asm
Implement Spectre variant 2 workarounds for NXP PowerPC Book3E
processors.
Diana Craciun (11):
Add infrastructure to fixup branch predictor flush
Add macro to flush the branch predictor
Fix spectre_v2 mitigations reporting
Emulate SPRN_BUCSR register
Add nospectre_v2 command line
(i.e.the kernel
is entered), the branch predictor state is flushed.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/head_booke.h | 6 ++
arch/powerpc/kernel/head_fsl_booke.S | 15 +++
2 files changed, 21 insertions(+)
diff --git a/arch/powerpc/kernel/head_booke.h b
-by: Diana Craciun
---
arch/powerpc/kvm/e500_emulate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index 3f8189e..d0eb670 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -276,6 +276,11
Fixed the following build warning:
powerpc-linux-gnu-ld: warning: orphan section `__btb_flush_fixup' from
`arch/powerpc/kernel/head_44x.o' being placed in section
`__btb_flush_fixup'.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/head_booke.h | 18 --
1 file changed, 12
When the command line argument is present, the Spectre variant 2
mitigations are disabled.
Signed-off-by: Diana Craciun
---
arch/powerpc/include/asm/setup.h | 5 +
arch/powerpc/kernel/security.c | 21 +
2 files changed, 26 insertions(+)
diff --git a/arch/powerpc
(i.e. the
kernel is entered), the branch predictor state is flushed.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/entry_64.S | 5 +
arch/powerpc/kernel/exceptions-64e.S | 26 +-
arch/powerpc/mm/tlb_low_64e.S| 7 +++
3 files changed, 37
Switching from the guest to host is another place
where the speculative accesses can be exploited.
Flush the branch predictor when entering KVM.
Signed-off-by: Diana Craciun
---
arch/powerpc/kvm/bookehv_interrupts.S | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/kvm
Currently for CONFIG_PPC_FSL_BOOK3E
cat /sys/devices/system/cpu/vulnerabilities/spectre_v2 reports:
"Mitigation: Software count cache flush" which is wrong. Fix it
to report vulnerable for now.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/security.c | 2 +-
1 file changed, 1
depending on a boot arg parameter which is added later in a
separate patch.
Signed-off-by: Diana Craciun
---
arch/powerpc/include/asm/feature-fixups.h | 12
arch/powerpc/include/asm/setup.h | 2 ++
arch/powerpc/kernel/vmlinux.lds.S | 8
arch/powerpc/lib
Signed-off-by: Diana Craciun
---
Documentation/admin-guide/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt
b/Documentation/admin-guide/kernel-parameters.txt
index aefd358..cf6b4c5 100644
If the user choses not to use the mitigations, replace
the code sequence with nops.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/setup-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 93ee370
Report branch predictor state flush as a mitigation for
Spectre variant 2.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/security.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 4393a38
Currently for CONFIG_PPC_FSL_BOOK3E
cat /sys/devices/system/cpu/vulnerabilities/spectre_v2 reports:
"Mitigation: Software count cache flush" which is wrong. Fix it
to report vulnerable for now.
Signed-off-by: Diana Craciun
---
v1->v2
- no change
arch/powerpc/kernel/security.c |
-by: Diana Craciun
---
v1-->v2
- no change
arch/powerpc/kvm/e500_emulate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index 3f8189e..d0eb670 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/
The BUCSR register can be used to invalidate the entries in the
branch prediction mechanisms.
Signed-off-by: Diana Craciun
---
v1-->v2
- no change
arch/powerpc/include/asm/ppc_asm.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc_asm.h
b/a
depending on a boot arg parameter which is added later in a
separate patch.
Signed-off-by: Diana Craciun
---
v1-->v2
- no change
arch/powerpc/include/asm/feature-fixups.h | 12
arch/powerpc/include/asm/setup.h | 2 ++
arch/powerpc/kernel/vmlinux.lds.S |
Report branch predictor state flush as a mitigation for
Spectre variant 2.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/kernel/security.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/ker
If the user choses not to use the mitigations, replace
the code sequence with nops.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/kernel/setup-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/se
When the command line argument is present, the Spectre variant 2
mitigations are disabled.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/include/asm/setup.h | 5 +
arch/powerpc/kernel/security.c | 21 +
2 files changed, 26 insertions(+)
d
Switching from the guest to host is another place
where the speculative accesses can be exploited.
Flush the branch predictor when entering KVM.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/kvm/bookehv_interrupts.S | 4
1 file changed, 4 insertions(+)
diff --
Implement Spectre variant 2 workarounds for NXP PowerPC Book3E
processors.
Diana Craciun (11):
Add infrastructure to fixup branch predictor flush
Add macro to flush the branch predictor
Fix spectre_v2 mitigations reporting
Emulate SPRN_BUCSR register
Add nospectre_v2 command line
(i.e.the kernel
is entered), the branch predictor state is flushed.
Signed-off-by: Diana Craciun
---
v1-->v2
- fixed warnings reported by the automated build system
arch/powerpc/kernel/head_booke.h | 11 +++
arch/powerpc/kernel/head_fsl_booke.S | 15 +++
2 files chan
(i.e. the
kernel is entered), the branch predictor state is flushed.
Signed-off-by: Diana Craciun
---
v1-->v2
- no change
arch/powerpc/kernel/entry_64.S | 5 +
arch/powerpc/kernel/exceptions-64e.S | 26 +-
arch/powerpc/mm/tlb_low_64e.S| 7 +++
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
Documentation/admin-guide/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt
b/Documentation/admin-guide/kernel-parameters.txt
index aefd358..cf6b
Hi Greg,
These are missing patches from the initial powerpc spectre backports for 4.4.
Please queue them as well if you don't have any objections.
Thanks,
Diana Craciun (8):
powerpc/fsl: Enable runtime patching if nospectre_v2 boot arg is used
powerpc/fsl: Flush branch predictor when
commit f633a8ad636efb5d4bba1a047d4a0f1ef719aa06 upstream.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/kernel-parameters.txt
b/Documentation/kernel
commit 3bc8ea8603ae4c1e09aca8de229ad38b8091fcb3 upstream.
If the user choses not to use the mitigations, replace
the code sequence with nops.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/setup_32.c | 1 +
arch/powerpc/kernel/setup_64.c | 1 +
2 files
commit e7aa61f47b23afbec41031bc47ca8d6cb6516abc upstream.
Switching from the guest to host is another place
where the speculative accesses can be exploited.
Flush the branch predictor when entering KVM.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kvm
just return as soon as possible
to guest.
Signed-off-by: Diana Craciun
[mpe: Tweak comment formatting]
Signed-off-by: Michael Ellerman
---
arch/powerpc/kvm/e500_emulate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
attacking the kernel
Basically when the privillege level change (i.e.the kernel
is entered), the branch predictor state is flushed.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/head_booke.h | 6 ++
arch/powerpc/kernel/head_fsl_booke.S | 15
commit c28218d4abbf4f2035495334d8bfcba64bda4787 upstream.
Used barrier_nospec to sanitize the syscall table.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/entry_32.S | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kernel
commit 039daac5526932ec731e4499613018d263af8b3e upstream.
Fixed the following build warning:
powerpc-linux-gnu-ld: warning: orphan section `__btb_flush_fixup' from
`arch/powerpc/kernel/head_44x.o' being placed in section
`__btb_flush_fixup'.
Signed-off-by: Diana Craciun
Signed-off-by: Michael
Currently only supported on powerpc.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
Documentation/kernel-parameters.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/kernel-parameters.txt
b/Documentation/kernel-parameters.txt
index f0bdf78420a0
commit 26cb1f36c43ee6e89d2a9f48a5a7500d5248f836 upstream.
Currently only supported on powerpc.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
Documentation/kernel-parameters.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/kernel-parameters.txt
b
commit e59f5bd759b7dee57593c5b6c0441609bda5d530 upstream.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/kernel-parameters.txt
b/Documentation/kernel
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