[PATCH] Disable /dev/port interface on powerpc systems

is causing the system crash. This patch will fix this issue by not creating this interface on these powerpc systems. Signed-off-by: Haren Myneni ha...@us.ibm.com diff -Naurp linux.orig/arch/powerpc/include/asm/io.h linux/arch/powerpc/include/asm/io.h --- linux.orig/arch/powerpc/include/asm

[PATCH] powerpc: SMT priority (PPR) save and restore

value whenever some register is available to use and then calls HMT_MEDIUM to increase the priority. This feature supports on P7 or later processors. Signed-off-by: Haren Myneni hb...@us.ibm.com diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 50d82c8

Re: [PATCH] powerpc: SMT priority (PPR) save and restore

processors. Signed-off-by: Haren Myneni hb...@us.ibm.com Can you break this patch into a few parts that are easier to review than one giant patch. Start by adding the PPR ftr bits, then the extra space in the paca, then the new macros, then use the new infrastructure. I'm sure you can get 5

Re: [PATCH] powerpc: Fix audit crash due to save/restore PPR changes

it: commit 44e9309f1f357794b7ae93d5f3e3e6f11d2b8a7f Author: Haren Myneni ha...@linux.vnet.ibm.com powerpc: Implement PPR save/restore It was found this patch corrupted r9 when calling SET_DEFAULT_THREAD_PPR() Using r10 as a scratch register instead of r9 solved the problem. Thanks for fixing

Change MINSIGSTKSZ and SIGSTKSIZE

Alan, LTP test (signalstack02) is failing. This test expects -ENOMEM from kernel when passing less than stack size (passing 4095). MINSIGSTKSZ in signal.h (glibc) is changed to 4096 to support VSX changes

[PATCH 0/6] powerpc: SMT priority (PPR) save and restore

exceptions without saving the user defined priorities when the task enters the kernel. So we will be loosing the process PPR value and can not be restored it back when the task exits the kernel. This patch set implements saving and restore the user defined PPR value for all tasks. Haren Myneni (6

[PATCH 1/6] powerpc: Move branch instruction from ACCOUNT_CPU_USER_ENTRY to caller

The first instruction in ACCOUNT_CPU_USER_ENTRY is 'beq' which checkes for exceptions coming from kernel mode. PPR value will be saved immediately after ACCOUNT_CPU_USER_ENTRY and is also for user level exceptions. So moved this branch instruction in the caller code. Signed-off-by: Haren Myneni

[PATCH 2/6] powerpc: Add enable_ppr kernel parameter to enable PPR save/restore

enable_ppr kernel parameter is used to enable PPR save and restore. Supported on Power7 and later processors. By default, CPU_FTR_HAS_PPR is set for POWER7. If this parameter is not passed, disable CPU_FTR_HAS_PPR. Signed-off-by: Haren Myneni ha...@us.ibm.com --- Documentation/kernel

[PATCH 3/6] powerpc: Add ppr in thread_info struct

ppr in thread_info is used to save PPR and restore it before process exits from kernel. This patch sets the default priority to 3 when tasks are created such that users can use 4 for higher priority tasks. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/thread_info.h

[PATCH 4/6] powerpc: Increase exceptions arrays in paca struct to save PPR

Using paca to save user defined PPR value in the first level exception vector. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h |1 + arch/powerpc/include/asm/paca.h |6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git

[PATCH 5/6] powerpc: Macros for saving/restore PPR

Several macros are defined for saving and restore user defined PPR value. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h | 35 ++ arch/powerpc/include/asm/reg.h |1 + 2 files changed, 36 insertions(+) diff

[PATCH 6/6] powerpc: Implement PPR save/restore

. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h | 12 +++- arch/powerpc/kernel/entry_64.S |4 arch/powerpc/kernel/exceptions-64s.S | 18 ++ 3 files changed, 21 insertions(+), 13 deletions(-) diff --git

Re: [PATCH 5/6] powerpc: Macros for saving/restore PPR

On 09/09/2012 09:24 PM, Benjamin Herrenschmidt wrote: On Sun, 2012-09-09 at 04:43 -0700, Haren Myneni wrote: Several macros are defined for saving and restore user defined PPR value. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h | 35

Re: [PATCH 1/6] powerpc: Move branch instruction from ACCOUNT_CPU_USER_ENTRY to caller

On 09/09/2012 05:05 PM, Benjamin Herrenschmidt wrote: On Sun, 2012-09-09 at 04:36 -0700, Haren Myneni wrote: The first instruction in ACCOUNT_CPU_USER_ENTRY is 'beq' which checkes for exceptions coming from kernel mode. PPR value will be saved immediately after ACCOUNT_CPU_USER_ENTRY

Re: [PATCH 2/6] powerpc: Add enable_ppr kernel parameter to enable PPR save/restore

On 09/09/2012 05:22 PM, Michael Neuling wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote: On Sun, 2012-09-09 at 04:37 -0700, Haren Myneni wrote: enable_ppr kernel parameter is used to enable PPR save and restore. Supported on Power7 and later processors. By default

[PATCH 0/6] powerpc: SMT priority (PPR) save and restore

defined PPR value for all tasks. With null_syscall testcase (http://ozlabs.org/~anton/junkcode/null_syscall.c), this feature takes around extra 10 CPU cycles on average for 25 samples. Haren Myneni (6): powerpc: Move branch instruction from ACCOUNT_CPU_USER_ENTRY to caller powerpc: Define

[PATCH 1/6] powerpc: Move branch instruction from ACCOUNT_CPU_USER_ENTRY to caller

. So moved this branch instruction in the caller code. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h |3 ++- arch/powerpc/include/asm/ppc_asm.h |2 -- arch/powerpc/kernel/entry_64.S |3 ++- arch/powerpc/kernel/exceptions-64e.S

[PATCH 2/6] powerpc: Define CPU_FTR_HAS_PPR

[PATCH 2/6] powerpc: Define CPU_FTR_HAS_PPR CPU_FTR_HAS_PPR is defined for POWER7. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/cputable.h |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch

[PATCH 3/6] powerpc: Increase exceptions arrays in paca struct to save PPR

[PATCH 3/6] powerpc: Increase exceptions arrays in paca struct to save PPR Using paca to save user defined PPR value in the first level exception vector. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h |1 + arch/powerpc/include/asm/paca.h

[PATCH 4/6] powerpc: Define ppr in thread_struct

[PATCH 4/6] powerpc: Define ppr in thread_struct ppr in thread_struct is used to save PPR and restore it before process exits from kernel. This patch sets the default priority to 3 when tasks are created such that users can use 4 for higher priority tasks. Signed-off-by: Haren Myneni ha

[PATCH 5/6] powerpc: Macros for saving/restore PPR

[PATCH 5/6] powerpc: Macros for saving/restore PPR Several macros are defined for saving and restore user defined PPR value. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h | 29 + arch/powerpc/include/asm/ppc_asm.h

[PATCH 6/6] powerpc: Implement PPR save/restore

. This feature supports on P7 or later processors. We save/ restore PPR for all exception vectors except system call entry. GLIBC will be saving / restore for system calls. So the default PPR value (3) will be set for the system call exit when the task returned to the user space. Signed-off-by: Haren

Re: [PATCH 2/6] powerpc: Define CPU_FTR_HAS_PPR

On 10/31/2012 06:25 AM, Kumar Gala wrote: On Oct 31, 2012, at 1:52 AM, Haren Myneni wrote: [PATCH 2/6] powerpc: Define CPU_FTR_HAS_PPR CPU_FTR_HAS_PPR is defined for POWER7. Would be nice if commit message spelled out what PPR is. Thanks, First patch described what PPR is. Agree, I

Re: [PATCH 0/6] powerpc: SMT priority (PPR) save and restore

On 10/31/2012 05:44 PM, Michael Neuling wrote: Haren Myneni ha...@linux.vnet.ibm.com wrote: [PATCH 0/6] powerpc: SMT priority (PPR) save and restore On P7 systems, users can define SMT priority levels 2,3 and 4 for processes so that some can run higher priority than the other ones

Re: [PATCH 2/6] powerpc: Define CPU_FTR_HAS_PPR

On 11/22/2012 08:01 PM, Michael Neuling wrote: Heaven Myneni ha...@linux.vnet.ibm.com wrote: [PATCH 2/6] powerpc: Define CPU_FTR_HAS_PPR CPU_FTR_HAS_PPR is defined for POWER7. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/cputable.h |6 -- 1 files

Re: [PATCH 5/6] powerpc: Macros for saving/restore PPR

On 11/22/2012 07:39 PM, Michael Neuling wrote: Haren Myneni ha...@linux.vnet.ibm.com wrote: [PATCH 5/6] powerpc: Macros for saving/restore PPR Several macros are defined for saving and restore user defined PPR value. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include

[PATCH 0/6] powerpc: SMT priority (PPR) save and restore

takes around extra 10 CPU cycles on average for 25 samples. Haren Myneni (6): powerpc: Move branch instruction from ACCOUNT_CPU_USER_ENTRY to caller powerpc: Enable PPR save/restore powerpc: Increase exceptions arrays in paca struct to save PPR powerpc: Define ppr in thread_struct powerpc

[PATCH 1/6] powerpc: Move branch instruction from ACCOUNT_CPU_USER_ENTRY to caller

. So moved this branch instruction in the caller code. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h |3 ++- arch/powerpc/include/asm/ppc_asm.h |2 -- arch/powerpc/kernel/entry_64.S |3 ++- arch/powerpc/kernel/exceptions-64e.S

[PATCH 2/6] powerpc: Enable PPR save/restore

[PATCH 2/6] powerpc: Enable PPR save/restore SMT thread status register (PPR) is used to set thread priority. This patch enables PPR save/restore feature (CPU_FTR_HAS_PPR) on POWER7 and POWER8 systems. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/cputable.h |7

[PATCH 3/6] powerpc: Increase exceptions arrays in paca struct to save PPR

[PATCH 3/6] powerpc: Increase exceptions arrays in paca struct to save PPR Using paca to save user defined PPR value in the first level exception vector. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h |1 + arch/powerpc/include/asm/paca.h

[PATCH 4/6] powerpc: Define ppr in thread_struct

[PATCH 4/6] powerpc: Define ppr in thread_struct ppr in thread_struct is used to save PPR and restore it before process exits from kernel. This patch sets the default priority to 3 when tasks are created such that users can use 4 for higher priority tasks. Signed-off-by: Haren Myneni ha

[PATCH 5/6] powerpc: Macros for saving/restore PPR

[PATCH 5/6] powerpc: Macros for saving/restore PPR Several macros are defined for saving and restore user defined PPR value. Signed-off-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h | 37 ++ arch/powerpc/include/asm/ppc_asm.h

[PATCH 6/6] powerpc: Implement PPR save/restore

-by: Haren Myneni ha...@us.ibm.com --- arch/powerpc/include/asm/exception-64s.h | 18 ++ arch/powerpc/kernel/entry_64.S |3 +++ arch/powerpc/kernel/exceptions-64s.S | 23 +-- 3 files changed, 26 insertions(+), 18 deletions(-) diff --git a/arch

mm: BUG_ON with NUMA_BALANCING (kernel BUG at include/linux/swapops.h:131!)

Hi, I am getting BUG_ON in migration_entry_to_page() with 4.1.0-rc2 kernel on powerpc system which has 512 CPUs (64 cores - 16 nodes) and 1.6 TB memory. We can easily recreate this issue with kernel compile (make -j500). But I could not reproduce with numa_balancing=disable. [ cut

Re: mm: BUG_ON with NUMA_BALANCING (kernel BUG at include/linux/swapops.h:131!)

On 5/14/15, Mel Gorman mgor...@suse.de wrote: On Wed, May 13, 2015 at 01:17:54AM -0700, Haren Myneni wrote: Hi, I am getting BUG_ON in migration_entry_to_page() with 4.1.0-rc2 kernel on powerpc system which has 512 CPUs (64 cores - 16 nodes) and 1.6 TB memory. We can easily recreate

Re: mm: BUG_ON with NUMA_BALANCING (kernel BUG at include/linux/swapops.h:131!)

On 5/18/15, Mel Gorman mgor...@suse.de wrote: On Mon, May 18, 2015 at 12:32:29AM -0700, Haren Myneni wrote: Mel, I am hitting this issue with 4.0 kernel and even with 3.19 and 3.17 kernels. I will also try with previous versions. Please let me know any suggestions on the debugging

Re: mm: BUG_ON with NUMA_BALANCING (kernel BUG at include/linux/swapops.h:131!)

Mel, I am hitting this issue with 4.0 kernel and even with 3.19 and 3.17 kernels. I will also try with previous versions. Please let me know any suggestions on the debugging. Thanks Haren On 5/14/15, Haren Myneni hmyn...@gmail.com wrote: On 5/14/15, Mel Gorman mgor...@suse.de wrote: On Wed

Re: [PATCH 3/3] powerpc/mm: Change the swap encoding in pte.

Tested this patch on 16TB system and fixed the BUG_ON issue mentioned here - https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-May/128767.html I was able to reproduce this issue in all previous releases (tested from 3.14). So this patch should be also in stable tree. Acked-by: Haren Myneni hb

crypto/nx842: Ignore queue overflow informative error

NX842 coprocessor sets bit 3 if queue is overflow. It is just for information to the user. So the driver prints this informative message and ignores it. Signed-off-by: Haren Myneni <ha...@us.ibm.com> diff --git a/arch/powerpc/include/asm/icswx.h b/arch/powerpc/include/asm/icswx.h

[PATCH] crypto/nx842: Mask XERS0 bit in return value

NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is nothing to do with NX request. Since this bit can be set with other valuable return status, mast this bit. One of other bits (INITIATED, BUSY or REJECTED) will be returned for any given NX request. Signed-off-by: Haren Myneni

Re: crypto/nx842: Ignore queue overflow informative error

On 12/07/2015 11:34 AM, Dan Streetman wrote: > On Sun, Dec 6, 2015 at 2:46 AM, Haren Myneni <ha...@linux.vnet.ibm.com> wrote: >> >> NX842 coprocessor sets bit 3 if queue is overflow. It is just for >> information to the user. So the driver prints this informa

Crypto/nx842: Ignore invalid XER[S0] return error

] value. One of other bits (INITIATED, BUSY or REJECTED) will be returned for any given NX request. Signed-off-by: Haren Myneni <ha...@us.ibm.com> diff --git a/arch/powerpc/include/asm/icswx.h b/arch/powerpc/include/asm/icswx.h index 9f8402b..27e588f 100644 --- a/arch/powerpc/include/asm/icswx.h

Re: Crypto/nx842: Ignore invalid XER[S0] return error

On 12/12/2015 04:05 PM, Segher Boessenkool wrote: > On Sat, Dec 12, 2015 at 03:01:26PM -0800, Haren Myneni wrote: >> On 12/12/2015 12:43 AM, Segher Boessenkool wrote: >>> On Fri, Dec 11, 2015 at 07:30:29PM -0800, Haren Myneni wrote: >>>> NX842 coprocessor sets 3rd

Re: Crypto/nx842: Ignore invalid XER[S0] return error

On 12/12/2015 12:43 AM, Segher Boessenkool wrote: > On Fri, Dec 11, 2015 at 07:30:29PM -0800, Haren Myneni wrote: >> NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is >> nothing to do with NX request. On powerpc, XER[S0] will be set if >> overflow in FPU an

Re: [PATCH 1/5] crypto/nx: Rename nx842_powernv_function as icswx function

On 04/04/2017 04:11 AM, Michael Ellerman wrote: > Haren Myneni <ha...@linux.vnet.ibm.com> writes: > >> [PATCH 1/5] crypto/nx: Rename nx842_powernv_function as icswx function >> >> nx842_powernv_function is points to nx842_icswx_function and >> will be point

[PATCH 0/5] crypto/nx: Enable NX 842 compression engine on Power9

to freeing co-processor structs for initialization failures and exit, both send and receive windows have to closed for VAS. The last 2 patches adds configuring and invoking VAS, and also checking P9 NX specific errors that are provided in co-processor status block (CSB) for failures. Haren

[PATCH 1/5] crypto/nx: Rename nx842_powernv_function as icswx function

[PATCH 1/5] crypto/nx: Rename nx842_powernv_function as icswx function nx842_powernv_function is points to nx842_icswx_function and will be point to VAS function which will be added later for P9 NX support. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-pow

[PATCH 2/5] crypto/nx: Create nx842_cfg_crb function

[PATCH 2/5] crypto/nx: Create nx842_cfg_crb function Configure CRB is moved to nx842_cfg_crb() so that it can be used for icswx function and VAS function which will be added later. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.

[PATCH 3/5] crypto/nx: Create nx842_delete_coproc function

[PATCH 3/5] crypto/nx: Create nx842_delete_coproc function Move deleting coprocessor info upon exit or failure to nx842_delete_coproc(). Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 25 - 1 file changed, 12 insertions(

[PATCH 4/5] crypto/nx: Add P9 NX support for 842 compression engine.

requests, we use only hight priority FIFOs in kernel. Each NX request will be communicated to VAS using copy/paste instructions with vas_copy_crb() / vas_paste_crb() functions. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- arch/powerpc/include/asm/vas.h | 2 + drivers/crypto/nx/K

[RESEND PATCH 0/5] Enable NX 842 compression engine on Power9

and testing with VAS changes. Haren Myneni (5): crypto/nx: Rename nx842_powernv_function as icswx function crypto/nx: Create nx842_cfg_crb function crypto/nx: Create nx842_delete_coproc function crypto/nx: Add P9 NX support for 842 compression engine. crypto/nx: Add P9 NX specific error codes

[PATCH 5/5] crypto/nx: Add P9 NX specific error codes for 842 engine

[PATCH 5/5] crypto/nx: Add P9 NX specific error codes for 842 engine This patch adds changes for checking P9 specific 842 engine error codes. These errros are reported in co-processor status block (CSB) for failures. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- arch/powerpc/inclu

Re: [PATCH 4/5] crypto/nx: Add P9 NX support for 842 compression engine.

Michael, Thanks for the review and comments. On 04/04/2017 03:55 AM, Michael Ellerman wrote: > Hi Haren, > > A few comments ... > > Haren Myneni <ha...@linux.vnet.ibm.com> writes: > >> diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/v

[PATCH V2 4/6] crypto/nx: Add nx842_add_coprocs_list function

Updating coprocessor list is moved to nx842_add_coprocs_list(). This function will be used for both icswx and VAS functions. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff

[PATCH V2 0/6] Enable NX 842 compression engine on Power9

such as priority and compatible properties. - Incorporate review comments from Michael Ellerman. - Other minor issues found during HW testing. Haren Myneni (6): crypto/nx842: Rename nx842_powernv_function as icswx function crypto/nx: Create nx842_configure_crb function crypto

[PATCH V2 5/6] crypto/nx: Add P9 NX specific error codes for 842 engine

This patch adds changes for checking P9 specific 842 engine error codes. These errros are reported in coprocessor status block (CSB) for failures. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- arch/powerpc/include/asm/icswx.h | 3 +++ drivers/crypto/nx/nx-842-powernv.

[PATCH V2 1/6] crypto/nx842: Rename nx842_powernv_function as icswx function

Rename nx842_powernv_function to nx842_powernv_exec. nx842_powernv_exec points to nx842_exec_icswx and will be point to VAS exec function which will be added later for P9 NX support. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.

[PATCH V2 2/6] crypto/nx: Create nx842_configure_crb function

Configure CRB is moved to nx842_configure_crb() so that it can be used for icswx and VAS exec functions. VAS function will be added later with P9 support. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 57 +-

[PATCH V2 3/6] crypto/nx: Create nx842_delete_coprocs function

Move deleting coprocessors info upon exit or failure to nx842_delete_coprocs(). Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/nx/

[PATCH V2 6/6] crypto/nx: Add P9 NX support for 842 compression engine

. For compression / decompression requests, we use only hight priority FIFOs in kernel. Each NX request will be communicated to VAS using copy/paste instructions with vas_copy_crb() / vas_paste_crb() functions. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/Kconfig

Re: [PATCH V2 0/6] Enable NX 842 compression engine on Power9

On 07/18/2017 11:06 AM, Sukadev Bhattiprolu wrote: > Nicholas Piggin [nicholas.pig...@gmail.com] wrote: >> On Mon, 17 Jul 2017 16:43:19 -0700 >> Haren Myneni <ha...@linux.vnet.ibm.com> wrote: >> >>> [PATCH V2 0/6] Enable NX 842 compression engine on Power9 >

Re: [PATCH V2 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 07/17/2017 11:53 PM, Ram Pai wrote: > On Mon, Jul 17, 2017 at 04:50:38PM -0700, Haren Myneni wrote: >> >> This patch adds P9 NX support for 842 compression engine. Virtual >> Accelerator Switchboard (VAS) is used to access 842 engine on P9. >> >> For each

[PATCH V3 2/6] crypto/nx: Create nx842_configure_crb function

Configure CRB is moved to nx842_configure_crb() so that it can be used for icswx and VAS exec functions. VAS function will be added later with P9 support. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 57 +-

[PATCH V3 4/6] crypto/nx: Add nx842_add_coprocs_list function

Updating coprocessor list is moved to nx842_add_coprocs_list(). This function will be used for both icswx and VAS functions. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff

[PATCH V3 3/6] crypto/nx: Create nx842_delete_coprocs function

Move deleting coprocessors info upon exit or failure to nx842_delete_coprocs(). Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/nx/

[PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

. For compression / decompression requests, we use only hight priority FIFOs in kernel. Each NX request will be communicated to VAS using copy/paste instructions with vas_copy_crb() / vas_paste_crb() functions. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/Kconfig

[PATCH V3 0/6] Enable NX 842 compression engine on Power9

in nx842_poernv_crypto_init/exit_vas(). - Changes for the new device-tree NX properties such as priority and compatible properties. - Incorporated review comments from Michael Ellerman. - Other minor issues found during HW testing. Haren Myneni (6): crypto/nx842: Rename

[PATCH V3 1/6] crypto/nx842: Rename nx842_powernv_function as icswx function

Rename nx842_powernv_function to nx842_powernv_exec. nx842_powernv_exec points to nx842_exec_icswx and will be point to VAS exec function which will be added later for P9 NX support. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.

[PATCH V3 5/6] crypto/nx: Add P9 NX specific error codes for 842 engine

This patch adds changes for checking P9 specific 842 engine error codes. These errros are reported in coprocessor status block (CSB) for failures. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- arch/powerpc/include/asm/icswx.h | 3 +++ drivers/crypto/nx/nx-842-powernv.

[PATCH 1/2] crypto/nx: Use percpu send window for NX requests

is executing. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 149 + 1 file changed, 68 insertions(+), 81 deletions(-) diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c index e

[PATCH 2/2] crypto/nx: Do not initialize workmem allocation

[PATCH 2/2] crypto/nx: Do not initialize workmem allocation We are using percpu send window on P9 NX (powerNV) instead of opening / closing per each crypto session. Means txwin is removed from workmem. So we do not need to initialize workmem for each request. Signed-off-by: Haren Myneni <

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 09/01/2017 04:34 AM, Michael Ellerman wrote: > Haren Myneni <ha...@linux.vnet.ibm.com> writes: >>> On Mon, Aug 28, 2017 at 7:25 PM, Michael Ellerman <m...@ellerman.id.au> >>> wrote: >>>> Hi Haren, >>>> >>>> Some comment

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 09/01/2017 04:29 AM, Michael Ellerman wrote: > Hi Dan, > > Thanks for reviewing this series. > > Dan Streetman <ddstr...@ieee.org> writes: >> On Tue, Aug 29, 2017 at 5:54 PM, Haren Myneni <ha...@linux.vnet.ibm.com> >> wrote: >>> On 0

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 08/29/2017 06:58 AM, Dan Streetman wrote: > On Sat, Jul 22, 2017 at 1:01 AM, Haren Myneni <ha...@linux.vnet.ibm.com> > wrote: >> >> This patch adds P9 NX support for 842 compression engine. Virtual >> Accelerator Switchboard (VAS) is used to access 842 engine o

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 08/29/2017 02:57 PM, Benjamin Herrenschmidt wrote: > On Tue, 2017-08-29 at 14:54 -0700, Haren Myneni wrote: >> Opening send window for each crypto transform (crypto_alloc, >> compression/decompression, ..., crypto_free) so that does not have to >> wait for the previous cop

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 09/02/2017 09:17 AM, Dan Streetman wrote: > On Sat, Sep 2, 2017 at 4:40 AM, Haren Myneni <ha...@linux.vnet.ibm.com> wrote: >> On 08/29/2017 06:58 AM, Dan Streetman wrote: >>> On Sat, Jul 22, 2017 at 1:01 AM, Haren Myneni <ha...@linux.vnet.ibm.com> >>>

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 08/31/2017 06:40 AM, Dan Streetman wrote: > On Thu, Aug 31, 2017 at 3:44 AM, Haren Myneni <ha...@linux.vnet.ibm.com> > wrote: >> Thanks MIchael and Dan for your review comments. >> >> >> On 08/29/2017 06:32 AM, Dan Streetman wrote: >>> On Mon,

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 08/31/2017 06:31 AM, Dan Streetman wrote: > On Tue, Aug 29, 2017 at 5:54 PM, Haren Myneni <ha...@linux.vnet.ibm.com> > wrote: >> On 08/29/2017 02:23 PM, Benjamin Herrenschmidt wrote: >>> On Tue, 2017-08-29 at 09:58 -0400, Dan Streetman wrote: >>

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

On 08/29/2017 02:23 PM, Benjamin Herrenschmidt wrote: > On Tue, 2017-08-29 at 09:58 -0400, Dan Streetman wrote: >>> + >>> + ret = -EINVAL; >>> + if (coproc && coproc->vas.rxwin) { >>> + wmem->txwin = nx842_alloc_txwin(coproc); >> >> this is wrong. the workmem is scratch

[PATCH V4 7/7] crypto/nx: Add P9 NX support for 842 compression engine

. For compression / decompression requests, we use only hight priority FIFOs in kernel. Each NX request will be communicated to VAS using copy/paste instructions with vas_copy_crb() / vas_paste_crb() functions. Signed-off-by: Haren Myneni <ha...@us.ibm.com> Reviewed-by: Ram Pai <linux...@u

[PATCH V4 1/7] crypto/nx: Rename nx842_powernv_function as icswx function

Rename nx842_powernv_function to nx842_powernv_exec. nx842_powernv_exec points to nx842_exec_icswx and will be point to VAS exec function which will be added later for P9 NX support. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.

[PATCH V4 6/7] crypto/nx: Add P9 NX specific error codes for 842 engine

This patch adds changes for checking P9 specific 842 engine error codes. These errros are reported in coprocessor status block (CSB) for failures. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- arch/powerpc/include/asm/icswx.h | 3 +++ drivers/crypto/nx/nx-842-powernv.

[PATCH V4 5/7] crypto/nx: Use kzalloc for workmem allocation

Send window is opened / closed for each crypto session. So initializes txwin in workmem. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/nx/nx-842.c b/drivers/crypto/nx/nx

[PATCH V4 3/7] crypto/nx: Create nx842_delete_coprocs function

Move deleting coprocessors info upon exit or failure to nx842_delete_coprocs(). Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/nx/

[PATCH V4 4/7] crypto/nx: Add nx842_add_coprocs_list function

Updating coprocessor list is moved to nx842_add_coprocs_list(). This function will be used for both icswx and VAS functions. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff

Re: [PATCH V3 6/6] crypto/nx: Add P9 NX support for 842 compression engine

Thanks MIchael and Dan for your review comments. On 08/29/2017 06:32 AM, Dan Streetman wrote: > On Mon, Aug 28, 2017 at 7:25 PM, Michael Ellerman <m...@ellerman.id.au> wrote: >> Hi Haren, >> >> Some comments inline ... >> >> Haren Myneni <ha...@lin

[PATCH V4 2/7] crypto/nx: Create nx842_configure_crb function

Configure CRB is moved to nx842_configure_crb() so that it can be used for icswx and VAS exec functions. VAS function will be added later with P9 support. Signed-off-by: Haren Myneni <ha...@us.ibm.com> --- drivers/crypto/nx/nx-842-powernv.c | 57 +-

[PATCH V4 0/7] Enable NX 842 compression engine on Power9

and compatible properties. - Incorporated review comments from Michael Ellerman. - Other minor issues found during HW testing. Haren Myneni (7): crypto/nx: Rename nx842_powernv_function as icswx function crypto/nx: Create nx842_configure_crb function crypto/nx: Create nx842_delete_coprocs

Re: [PATCH][V2] crypto/nx: fix spelling mistake: "availavle" -> "available"

Sorry for my mistake. Thanks. Acked-by: Haren Myneni <ha...@us.ibm.com> On 11/14/2017 06:32 AM, Colin King wrote: > From: Colin Ian King <colin.k...@canonical.com> > > Trivial fix to spelling mistake in pr_err error message text. Also > fix spelling mistake in proceed

Re: [rfc] powernv/kdump: Fix cases where the kdump kernel can get HMI's

On 12/05/2017 08:29 PM, Balbir Singh wrote: > On Mon, Dec 4, 2017 at 2:10 PM, Nicholas Piggin wrote: >> On Mon, 4 Dec 2017 11:37:01 +1100 >> Balbir Singh wrote: >> >>> On Sun, Dec 3, 2017 at 1:36 PM, Nicholas Piggin wrote: Seems

Re: [PATCH] powerpc: paste - Mask XERSO bit in CR

On 04/26/2018 11:27 PM, Michael Ellerman wrote: > Haren Myneni <ha...@linux.vnet.ibm.com> writes: >> >> NX can set 3rd bit in CR register for XER[SO] (Summation overflow) >> which is not used for paste return value. So. mask this bit to get >> proper return st

[PATCH V3 1/2] powerpc/powernv: Export opal_check_token symbol

Export opal_check_token symbol for modules to check the availability of OPAL calls before using them. Signed-off-by: Haren Myneni diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c index 48fbb41..838b79b 100644 --- a/arch/powerpc/platforms/powernv

[PATCH V3 2/2] crypto/nx: Initialize 842 high and normal RxFIFO control registers

. Signed-off-by: Haren Myneni --- Changlog: V2: Execute nx_coproc_init OPAL call per NX without depending on FIFO priority [Stewart Smith] V3: Verify OPAL call availability before using NX coproc init [Michael Ellerman] diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include

powerpc/powernv: copy/paste - Mask XERS0 bit in CR

v/vas: Define copy/paste interfaces") Cc: sta...@vger.kernel.org # v4.14+ Signed-off-by: Haren Myneni diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h index c9a5036..82392e3 100644 --- a/arch/powerpc/platforms/powernv/copy-paste.h

[PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

. Signed-off-by: Haren Myneni diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h index d886a5b..ff61e4b 100644 --- a/arch/powerpc/include/asm/opal-api.h +++ b/arch/powerpc/include/asm/opal-api.h @@ -206,7 +206,8 @@ #define OPAL_NPU_TL_SET

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

On 06/03/2018 05:41 PM, Stewart Smith wrote: > Haren Myneni writes: >> On 06/01/2018 12:41 AM, Stewart Smith wrote: >>> Haren Myneni writes: >>>> NX increments readOffset by FIFO size in receive FIFO control register >>>> when CRB is

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

On 06/03/2018 09:08 PM, Stewart Smith wrote: > Haren Myneni writes: >> On 06/03/2018 05:41 PM, Stewart Smith wrote: >>> Haren Myneni writes: >>>> On 06/01/2018 12:41 AM, Stewart Smith wrote: >>>>> Haren Myneni writes: >>>>>> NX incr

Re: powerpc/powernv: copy/paste - Mask XERS0 bit in CR

On 06/03/2018 03:48 AM, Michael Ellerman wrote: > Hi Haren, > > Haren Myneni writes: >> >> NX can set 3rd bit in CR register for XER[SO] (Summation overflow) >> which is not related to paste request. The current paste function >> returns failure for the

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

On 05/31/2018 08:52 PM, Stewart Smith wrote: > Haren Myneni writes: >> NX increments readOffset by FIFO size in receive FIFO control register >> when CRB is read. But the index in RxFIFO has to match with the >> corresponding entry in FIFO maintained by VAS in kernel

[PATCH V2] crypto/nx: Initialize 842 high and normal RxFIFO control registers

. Signed-off-by: Haren Myneni --- Changlog: V2: Execute nx_coproc_init OPAL call per NX without depending on FIFO priority [Stewart Smith] diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h index d886a5b..ff61e4b 100644 --- a/arch/powerpc/include/asm/opal-api.h

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