[PATCH] powerpc/powernv: Add mmap to opal export sysfs nodes

2019-04-03 Thread Jordan Niethe
on the current read/lseek method as it handles cases like the buffer wrapping and overflowing. Signed-off-by: Jordan Niethe --- v2: ensure only whole pages can be mapped --- arch/powerpc/platforms/powernv/opal.c | 12 1 file changed, 12 insertions(+) diff --git a/arch/powerpc/platforms

[PATCH] KVM: PPC: Book3S HV: Fix build failure without IOMMU support

2019-02-20 Thread Jordan Niethe
3S PR: Don't include SPAPR TCE code on non-pseries platforms") Signed-off-by: Jordan Niethe --- arch/powerpc/kvm/book3s_hv.c| 2 ++ arch/powerpc/kvm/book3s_hv_rmhandlers.S | 10 ++ 2 files changed, 12 insertions(+) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/p

[PATCH] powerpc/powernv: Make opal log only readable by root

2019-02-26 Thread Jordan Niethe
Currently the opal log is globally readable. It is kernel policy to limit the visibility of physical addresses / kernel pointers to root. Given this and the fact the opal log may contain this information it would be better to limit the readability to root. Signed-off-by: Jordan Niethe --- arch

[PATCH] powerpc/powernv: Add mmap to opal export sysfs nodes

2019-03-14 Thread Jordan Niethe
-by: Jordan Niethe --- arch/powerpc/platforms/powernv/opal.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c index 2b0eca104f86..3cfc683bb060 100644 --- a/arch/powerpc/platforms/powernv/opal.c +++ b/arch

Re: [PATCH v2 1/3] KVM: PPC: Book3S HV: Fix race in re-enabling XIVE escalation interrupts

2019-08-13 Thread Jordan Niethe
On Tue, 2019-08-13 at 20:03 +1000, Paul Mackerras wrote: > Escalation interrupts are interrupts sent to the host by the XIVE > hardware when it has an interrupt to deliver to a guest VCPU but that > VCPU is not running anywhere in the system. Hence we disable the > escalation interrupt for the

Re: [PATCH 1/3] powerpc/xmon: Check for HV mode when dumping XIVE info from OPAL

2019-08-15 Thread Jordan Niethe
On Wed, 2019-08-14 at 17:47 +0200, Cédric Le Goater wrote: > Currently, the xmon 'dx' command calls OPAL to dump the XIVE state in > the OPAL logs and also outputs some of the fields of the internal > XIVE > structures in Linux. The OPAL calls can only be done on baremetal > (PowerNV) and they

[PATCH] powerpc: Remove empty comment

2019-08-12 Thread Jordan Niethe
Commit 2874c5fd2842 ("treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152") left an empty comment in machdep.h, as the boilerplate was the only text in the comment. Remove the empty comment. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/machdep.h | 3 -

Re: [PATCH v4 7/9] powerpc/eeh: Add bdfn field to eeh_dev

2019-08-08 Thread Jordan Niethe
On Wed, 2019-08-07 at 13:44 +1000, Sam Bobroff wrote: > From: Oliver O'Halloran > > Preparation for removing pci_dn from the powernv EEH code. The only > thing we really use pci_dn for is to get the bdfn of the device for > config space accesses, so adding that information to eeh_dev reduces >

[PATCH] powerpc/xive: Update comment referencing magic loads from an ESB

2019-08-01 Thread Jordan Niethe
ive-regs.h Signed-off-by: Jordan Niethe --- arch/powerpc/sysdev/xive/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c index 1cdb39575eae..083f657091d7 100644 --- a/arch/powerpc/sysdev/xive/common.c

[PATCH] PPC: Set reserved PCR bits

2019-07-15 Thread Jordan Niethe
-off-by: Jordan Niethe --- arch/powerpc/include/asm/reg.h | 3 +++ arch/powerpc/kernel/cpu_setup_power.S | 6 ++ arch/powerpc/kernel/dt_cpu_ftrs.c | 3 ++- arch/powerpc/kvm/book3s_hv.c| 11 +++ arch/powerpc/kvm/book3s_hv_nested.c | 6 +++--- arch

[PATCH v2] powerpc/mm: Remove kvm radix prefetch workaround for Power9 DD2.2

2019-12-04 Thread Jordan Niethe
pu feature CPU_FTR_P9_RADIX_PREFETCH_BUG to indicate if the workarounds are needed. Signed-off-by: Jordan Niethe --- v2: Use a cpu feature instead of open coding the PVR check --- arch/powerpc/include/asm/cputable.h | 6 -- arch/powerpc/kernel/dt_cpu_ftrs.c| 13 - arch/p

[PATCH] powerpc/64: Use {SAVE,REST}_NVGPRS macros

2019-12-10 Thread Jordan Niethe
In entry_64.S there are places that open code saving and restoring the non-volatile registers. There are already macros for doing this so use them. Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/entry_64.S | 18 ++ 1 file changed, 6 insertions(+), 12 deletions(-) diff

[PATCH 1/2] powerpc/64s/exception: Remove unused parameters from KVMTEST macro

2019-12-10 Thread Jordan Niethe
The hsrr and n parameters are never used by the KVMTEST macro so remove them. Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/exceptions-64s.S | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel

[PATCH 2/2] powerpc/64s/exception: Add missing comma to INT_KVM_HANDLER macro for system_reset

2019-12-10 Thread Jordan Niethe
The INT_KVM_HANDLER macro for system_reset is missing a comma so add it to be consistent. Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/exceptions-64s.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel

Re: [PATCH v3 3/3] powerpc: Book3S 64-bit "heavyweight" KASAN support

2019-12-12 Thread Jordan Niethe
On Fri, Dec 13, 2019 at 2:19 AM Daniel Axtens wrote: > > KASAN support on Book3S is a bit tricky to get right: > > - It would be good to support inline instrumentation so as to be able to >catch stack issues that cannot be caught with outline mode. > > - Inline instrumentation requires a

[PATCH v3] powerpc/mm: Remove kvm radix prefetch workaround for Power9 DD2.2

2019-12-05 Thread Jordan Niethe
pu feature CPU_FTR_P9_RADIX_PREFETCH_BUG to indicate if the workarounds are needed. Signed-off-by: Jordan Niethe --- v2: Use a cpu feature instead of open coding the PVR check v3: Put parentheses around CPU_FTRS_POWER9_DD2_0 value --- arch/powerpc/include/asm/cputable.h | 7 +-- arch/powe

[PATCH 10/18] powerpc: Support prefixed instructions in alignment handler

2019-11-25 Thread Jordan Niethe
by 8. Prefixed instructions are not permitted to cross 64-byte boundaries. If they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set. If this occurs send a SIGBUS to the offending process if in user mode. If in kernel mode call bad_page_fault(). Signed-off-by: Jordan Niethe --- arch

[PATCH 13/18] powerpc/xmon: Dump prefixed instructions

2019-11-25 Thread Jordan Niethe
suffix is loaded too. Then print these in the form: prefix:suffix Xmon uses the disassembly routines from GNU binutils. These currently do not support prefixed instructions so we will not disassemble the prefixed instructions yet. Signed-off-by: Jordan Niethe --- arch/powerpc/xmon/xmon.c | 50

[PATCH 06/18] powerpc sstep: Add support for prefixed integer load/stores

2019-11-25 Thread Jordan Niethe
Doubleword (pld) * Prefixed Store Byte (pstb) * Prefixed Store Halfword (psth) * Prefixed Store Word (pstw) * Prefixed Store Doubleword (pstd) * Prefixed Load Quadword (plq) * Prefixed Store Quadword (pstq) Signed-off-by: Jordan Niethe --- arch/powerpc/lib/sstep.c | 110

[PATCH 09/18] powerpc sstep: Add support for prefixed fixed-point arithmetic

2019-11-25 Thread Jordan Niethe
This adds emulation support for the following prefixed Fixed-Point Arithmetic instructions: * Prefixed Add Immediate (paddi) Signed-off-by: Jordan Niethe --- arch/powerpc/lib/sstep.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c

[PATCH 11/18] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception()

2019-11-25 Thread Jordan Niethe
n() within facility_unavailable_exception(). However, when caused by a prefixed instructions the SRR1 PREFIXED bit is set. Prepare for dealing with emulated prefixed instructions by checking for this bit. Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/traps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/ar

[PATCH 04/18] powerpc: Rename Bit 35 of SRR1 to indicate new purpose

2019-11-25 Thread Jordan Niethe
from SRR1_ISI_N_OR_G -> SRR1_ISI_N_G_OR_CIP to reflected this new role. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/reg.h | 2 +- arch/powerpc/kvm/book3s_hv_nested.c | 2 +- arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --

[PATCH 16/18] powerpc/hw_breakpoints: Initial support for prefixed instructions

2019-11-25 Thread Jordan Niethe
Currently when getting an instruction to emulate in hw_breakpoint_handler() we do not load the suffix of a prefixed instruction. Ensure we load the suffix if the instruction we need to emulate is a prefixed instruction. Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/hw_breakpoint.c | 8

[PATCH 17/18] powerpc: Add prefix support to mce_find_instr_ea_and_pfn()

2019-11-25 Thread Jordan Niethe
mce_find_instr_ea_and_pfn analyses an instruction to determine the effective address that caused the machine check. Update this to load and pass the suffix to analyse_instr for prefixed instructions. Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/mce_power.c | 6 -- 1 file changed, 4

[PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

2019-11-25 Thread Jordan Niethe
are emulated or analysed - this is just making it possible to do so. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/ppc-opcode.h | 3 +++ arch/powerpc/include/asm/sstep.h | 8 +-- arch/powerpc/include/asm/uaccess.h| 30 +++ arch/powerpc/kernel/align.c

[PATCH 08/18] powerpc sstep: Add support for prefixed VSX load/stores

2019-11-25 Thread Jordan Niethe
Store VSX Scalar Single-Precision (pstxssp) * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1) Signed-off-by: Jordan Niethe --- arch/powerpc/lib/sstep.c | 42 1 file changed, 42 insertions(+) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib

[PATCH 07/18] powerpc sstep: Add support for prefixed floating-point load/stores

2019-11-25 Thread Jordan Niethe
This adds emulation support for the follow prefixed floating-point load/stores: * Prefixed Load Floating-Point Single (plfs) * Prefixed Load Floating-Point Double (plfd) * Prefixed Store Floating-Point Single (pstfs) * Prefixed Store Floating-Point Double (pstfd) Signed-off-by: Jordan

[PATCH 12/18] powerpc/xmon: Add initial support for prefixed instructions

2019-11-25 Thread Jordan Niethe
. No support for disassembling prefixed instructions. Signed-off-by: Jordan Niethe --- arch/powerpc/xmon/xmon.c | 82 ++-- 1 file changed, 71 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index f47bd843dc52

[PATCH 14/18] powerpc/kprobes: Support kprobes on prefixed instructions

2019-11-25 Thread Jordan Niethe
. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/kprobes.h | 5 +-- arch/powerpc/kernel/kprobes.c| 46 +--- arch/powerpc/kernel/optprobes.c | 31 +++ arch/powerpc/kernel/optprobes_head.S | 6 4 files changed, 62 insertions

[PATCH 15/18] powerpc/uprobes: Add support for prefixed instructions

2019-11-25 Thread Jordan Niethe
Uprobes can execute instructions out of line. Increase the size of the buffer used for this so that this works for prefixed instructions. Take into account the length of prefixed instructions when fixing up the nip. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/uprobes.h | 18

[PATCH 18/18] powerpc/fault: Use analyse_instr() to check for store with updates to sp

2019-11-25 Thread Jordan Niethe
and stores. So this patch is probably not needed but it might be preferable to use analyse_instr() rather than open coding the test anyway. Signed-off-by: Jordan Niethe --- arch/powerpc/mm/fault.c | 39 +++ 1 file changed, 11 insertions(+), 28 deletions(-) diff

[PATCH 02/18] powerpc: Add BOUNDARY SRR1 bit for future ISA version

2019-11-25 Thread Jordan Niethe
Add the bit definition for when the cause of an alignment exception is a prefixed instruction that crosses a 64-byte boundary. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/reg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc

[PATCH 00/18] Initial Prefixed Instruction support

2019-11-25 Thread Jordan Niethe
emulation to support them. Then the places where prefixed instructions might need to be emulated are updated. A future series will add prefixed instruction support to guests running in KVM. Alistair Popple (1): powerpc: Enable Prefixed Instructions Jordan Niethe (17): powerpc: Add BOUNDARY SRR1 bit

[PATCH 03/18] powerpc: Add PREFIXED SRR1 bit for future ISA version

2019-11-25 Thread Jordan Niethe
Add the bit definition for exceptions caused by prefixed instructions. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/reg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 6f9fcc3d4c82..0a6d39fb4769 100644

[PATCH 01/18] powerpc: Enable Prefixed Instructions

2019-11-25 Thread Jordan Niethe
From: Alistair Popple Prefix instructions have their own FSCR bit which needs to enabled via a CPU feature. The kernel will save the FSCR for problem state but it needs to be enabled initially. Signed-off-by: Alistair Popple --- arch/powerpc/include/asm/reg.h| 3 +++

[PATCH] powerpc/mm: Remove kvm radix prefetch workaround for Power9 DD2.2

2019-12-01 Thread Jordan Niethe
refetching for the hypervisor with that PID value. In Power9 DD2.2 the cpu behaviour was modified to fix this. When accessing Quadrant 0 in hypervisor mode with LPID != 0 prefetching will not be performed. This means that we can get rid of the workarounds for Power9 DD2.2 and later revisions. Signed-off-

[PATCH] powerpc/kvm: Fix kvmppc_vcore->in_guest value in kvmhv_switch_to_host

2019-10-03 Thread Jordan Niethe
Fix by making sure r0 is 0 before storing it to kvmppc_vcore->in_guest. Fixes: 13c7bb3c57dc ("powerpc/64s: Set reserved PCR bits") Reported-by: Alexey Kardashevskiy Signed-off-by: Jordan Niethe --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 1 + 1 file changed, 1 insertion(+

Re: [PATCH 03/18] powerpc: Add PREFIXED SRR1 bit for future ISA version

2019-12-19 Thread Jordan Niethe
On Wed, Dec 18, 2019 at 7:23 PM Daniel Axtens wrote: > > Jordan Niethe writes: > > > Add the bit definition for exceptions caused by prefixed instructions. > > > > Signed-off-by: Jordan Niethe > > --- > > arch/powerpc/include/asm/reg.h | 1 + > >

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

2019-12-19 Thread Jordan Niethe
On Wed, Dec 18, 2019 at 7:35 PM Daniel Axtens wrote: > > Jordan Niethe writes: > > > Currently all instructions are a single word long. A future ISA version > > will include prefixed instructions which have a double word length. The > > functions used for analysing

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

2019-12-19 Thread Jordan Niethe
On Thu, Dec 19, 2019 at 1:15 AM Daniel Axtens wrote: > > Jordan Niethe writes: > > > Currently all instructions are a single word long. A future ISA version > > will include prefixed instructions which have a double word length. The > > functions used for analysing

Re: [PATCH v2 06/13] powerpc: Support prefixed instructions in alignment handler

2020-02-11 Thread Jordan Niethe
On Tue, Feb 11, 2020 at 5:14 PM Christophe Leroy wrote: > > > > Le 11/02/2020 à 06:33, Jordan Niethe a écrit : > > Alignment interrupts can be caused by prefixed instructions accessing > > memory. In the alignment handler the instruction that caused the > > exc

Re: [PATCH v2 10/13] powerpc/kprobes: Support kprobes on prefixed instructions

2020-02-11 Thread Jordan Niethe
On Tue, Feb 11, 2020 at 5:46 PM Christophe Leroy wrote: > > > > Le 11/02/2020 à 06:33, Jordan Niethe a écrit : > > A prefixed instruction is composed of a word prefix followed by a word > > suffix. It does not make sense to be able to have a kprobe on the suffix > >

Re: [PATCH v2 09/13] powerpc/xmon: Dump prefixed instructions

2020-02-11 Thread Jordan Niethe
On Tue, Feb 11, 2020 at 5:39 PM Christophe Leroy wrote: > > > > Le 11/02/2020 à 06:33, Jordan Niethe a écrit : > > Currently when xmon is dumping instructions it reads a word at a time > > and then prints that instruction (either as a hex number or by > > d

Re: [PATCH v2 08/13] powerpc/xmon: Add initial support for prefixed instructions

2020-02-11 Thread Jordan Niethe
On Tue, Feb 11, 2020 at 5:32 PM Christophe Leroy wrote: > > > > Le 11/02/2020 à 06:33, Jordan Niethe a écrit : > > A prefixed instruction is composed of a word prefix and a word suffix. > > It does not make sense to be able to have a breakpoint on the suffix of > > a

Re: [PATCH v2 04/13] powerpc sstep: Add support for prefixed load/stores

2020-02-11 Thread Jordan Niethe
On Tue, Feb 11, 2020 at 5:05 PM Christophe Leroy wrote: > > > > Le 11/02/2020 à 06:33, Jordan Niethe a écrit : > > This adds emulation support for the following prefixed integer > > load/stores: > >* Prefixed Load Byte and Zero (plbz) > >* P

[PATCH v2 11/13] powerpc/uprobes: Add support for prefixed instructions

2020-02-10 Thread Jordan Niethe
Uprobes can execute instructions out of line. Increase the size of the buffer used for this so that this works for prefixed instructions. Take into account the length of prefixed instructions when fixing up the nip. Signed-off-by: Jordan Niethe --- v2: - Fix typo - Use macro for instruction

[PATCH v2 12/13] powerpc/hw_breakpoints: Initial support for prefixed instructions

2020-02-10 Thread Jordan Niethe
Currently when getting an instruction to emulate in hw_breakpoint_handler() we do not load the suffix of a prefixed instruction. Ensure we load the suffix if the instruction we need to emulate is a prefixed instruction. Signed-off-by: Jordan Niethe --- v2: Rename sufx to suffix --- arch/powerpc

[PATCH v2 03/13] powerpc sstep: Prepare to support prefixed instructions

2020-02-10 Thread Jordan Niethe
are emulated or analysed - this is just making it possible to do so. Signed-off-by: Jordan Niethe --- v2: - Move definition of __get_user_instr() and __get_user_instr_inatomic() to "powerpc: Support prefixed instructions in alignment handler." - Use a macro for returning the length of an op

[PATCH v2 04/13] powerpc sstep: Add support for prefixed load/stores

2020-02-10 Thread Jordan Niethe
-Precision (plxssp) * Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1) * Prefixed Store VSX Scalar Doubleword (pstxsd) * Prefixed Store VSX Scalar Single-Precision (pstxssp) * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1) Signed-off-by: Jordan Niethe --- v2: - Combine all load/store

[PATCH v2 08/13] powerpc/xmon: Add initial support for prefixed instructions

2020-02-10 Thread Jordan Niethe
. No support for disassembling prefixed instructions. Signed-off-by: Jordan Niethe --- v2: Rename sufx to suffix --- arch/powerpc/xmon/xmon.c | 82 ++-- 1 file changed, 71 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon

[PATCH v2 13/13] powerpc: Add prefix support to mce_find_instr_ea_and_pfn()

2020-02-10 Thread Jordan Niethe
mce_find_instr_ea_and_pfn analyses an instruction to determine the effective address that caused the machine check. Update this to load and pass the suffix to analyse_instr for prefixed instructions. Signed-off-by: Jordan Niethe --- v2: - Rename sufx to suffix --- arch/powerpc/kernel

[PATCH v2 07/13] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception()

2020-02-10 Thread Jordan Niethe
n() within facility_unavailable_exception(). However, when caused by a prefixed instructions the SRR1 PREFIXED bit is set. Prepare for dealing with emulated prefixed instructions by checking for this bit. Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/traps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/ar

[PATCH v2 05/13] powerpc sstep: Add support for prefixed fixed-point arithmetic

2020-02-10 Thread Jordan Niethe
This adds emulation support for the following prefixed Fixed-Point Arithmetic instructions: * Prefixed Add Immediate (paddi) Signed-off-by: Jordan Niethe --- arch/powerpc/lib/sstep.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c

[PATCH v2 06/13] powerpc: Support prefixed instructions in alignment handler

2020-02-10 Thread Jordan Niethe
by 8. Prefixed instructions are not permitted to cross 64-byte boundaries. If they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set. If this occurs send a SIGBUS to the offending process if in user mode. If in kernel mode call bad_page_fault(). Signed-off-by: Jordan Niethe --- v2

[PATCH v2 01/13] powerpc: Enable Prefixed Instructions

2020-02-10 Thread Jordan Niethe
From: Alistair Popple Prefix instructions have their own FSCR bit which needs to enabled via a CPU feature. The kernel will save the FSCR for problem state but it needs to be enabled initially. Signed-off-by: Alistair Popple --- arch/powerpc/include/asm/reg.h| 3 +++

[PATCH v2 00/13] Initial Prefixed Instruction support

2020-02-10 Thread Jordan Niethe
werpc: Enable Prefixed Instructions Jordan Niethe (12): powerpc: Define new SRR1 bits for a future ISA version powerpc sstep: Prepare to support prefixed instructions powerpc sstep: Add support for prefixed load/stores powerpc sstep: Add support for prefixed fixed-point arithmetic pow

[PATCH v2 02/13] powerpc: Define new SRR1 bits for a future ISA version

2020-02-10 Thread Jordan Niethe
used to indicate that an ISI was due to the access being no-exec or guarded. A future ISA version adds another purpose. It is also set if there is an access in a cache-inhibited location for prefixed instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP. Signed-off-by: Jordan Niethe

[PATCH v2 10/13] powerpc/kprobes: Support kprobes on prefixed instructions

2020-02-10 Thread Jordan Niethe
. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/kprobes.h | 5 +-- arch/powerpc/kernel/kprobes.c| 47 +--- arch/powerpc/kernel/optprobes.c | 32 ++- arch/powerpc/kernel/optprobes_head.S | 6 4 files changed, 63 insertions

[PATCH v2 09/13] powerpc/xmon: Dump prefixed instructions

2020-02-10 Thread Jordan Niethe
suffix is loaded too. Then print these in the form: prefix:suffix Xmon uses the disassembly routines from GNU binutils. These currently do not support prefixed instructions so we will not disassemble the prefixed instructions yet. Signed-off-by: Jordan Niethe --- v2: Rename sufx to suffix

[PATCH v3 08/14] powerpc/xmon: Remove store_inst() for patch_instruction()

2020-02-25 Thread Jordan Niethe
(). Otherwise replace store_inst() with patch_instruction(). Signed-off-by: Jordan Niethe --- arch/powerpc/xmon/xmon.c | 13 ++--- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 897e512c6379..a673cf55641c 100644 --- a/arch

[PATCH v3 09/14] powerpc/xmon: Add initial support for prefixed instructions

2020-02-25 Thread Jordan Niethe
. No support for disassembling prefixed instructions. Signed-off-by: Jordan Niethe --- v2: Rename sufx to suffix v3: - Just directly use PPC_INST_NOP - Typo: plac -> place - Rename read_inst() to mread_inst(). Do not have it call mread(). --- arch/powerpc/xmon/xmon.c |

[PATCH v3 11/14] powerpc/kprobes: Support kprobes on prefixed instructions

2020-02-25 Thread Jordan Niethe
. Signed-off-by: Jordan Niethe --- v3: - Base on top of https://patchwork.ozlabs.org/patch/1232619/ - Change printing format to %x:%x --- arch/powerpc/include/asm/kprobes.h | 5 ++-- arch/powerpc/kernel/kprobes.c| 43 +--- arch/powerpc/kernel/optprobes.c

[PATCH v3 10/14] powerpc/xmon: Dump prefixed instructions

2020-02-25 Thread Jordan Niethe
suffix is loaded too. Then print these in the form: prefix:suffix Xmon uses the disassembly routines from GNU binutils. These currently do not support prefixed instructions so we will not disassemble the prefixed instructions yet. Signed-off-by: Jordan Niethe --- v2: Rename sufx to suffix v3

[PATCH v3 02/14] powerpc: Define new SRR1 bits for a future ISA version

2020-02-25 Thread Jordan Niethe
used to indicate that an ISI was due to the access being no-exec or guarded. A future ISA version adds another purpose. It is also set if there is an access in a cache-inhibited location for prefixed instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP. Signed-off-by: Jordan Niethe

[PATCH v3 01/14] powerpc: Enable Prefixed Instructions

2020-02-25 Thread Jordan Niethe
From: Alistair Popple Prefix instructions have their own FSCR bit which needs to enabled via a CPU feature. The kernel will save the FSCR for problem state but it needs to be enabled initially. Signed-off-by: Alistair Popple --- arch/powerpc/include/asm/reg.h| 3 +++

[PATCH v3 13/14] powerpc/hw_breakpoints: Initial support for prefixed instructions

2020-02-25 Thread Jordan Niethe
Currently when getting an instruction to emulate in hw_breakpoint_handler() we do not load the suffix of a prefixed instruction. Ensure we load the suffix if the instruction we need to emulate is a prefixed instruction. Signed-off-by: Jordan Niethe --- v2: Rename sufx to suffix v3: Add __user

[PATCH v3 00/14] Initial Prefixed Instruction support

2020-02-25 Thread Jordan Niethe
orted by Greg Kurz did not work correctly. Alistair Popple (1): powerpc: Enable Prefixed Instructions Jordan Niethe (13): powerpc: Define new SRR1 bits for a future ISA version powerpc sstep: Prepare to support prefixed instructions powerpc sstep: Add support for prefixed load/stores power

[PATCH v3 05/14] powerpc sstep: Add support for prefixed fixed-point arithmetic

2020-02-25 Thread Jordan Niethe
This adds emulation support for the following prefixed Fixed-Point Arithmetic instructions: * Prefixed Add Immediate (paddi) Signed-off-by: Jordan Niethe --- v3: Since we moved the prefixed loads/stores into the load/store switch statement it no longer makes sense to have paddi in there, so

[PATCH v3 12/14] powerpc/uprobes: Add support for prefixed instructions

2020-02-25 Thread Jordan Niethe
Uprobes can execute instructions out of line. Increase the size of the buffer used for this so that this works for prefixed instructions. Take into account the length of prefixed instructions when fixing up the nip. Signed-off-by: Jordan Niethe --- v2: - Fix typo - Use macro for instruction

[PATCH v3 07/14] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception()

2020-02-25 Thread Jordan Niethe
n() within facility_unavailable_exception(). However, when caused by a prefixed instructions the SRR1 PREFIXED bit is set. Prepare for dealing with emulated prefixed instructions by checking for this bit. Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/traps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/ar

[PATCH v3 06/14] powerpc: Support prefixed instructions in alignment handler

2020-02-25 Thread Jordan Niethe
by 8. Prefixed instructions are not permitted to cross 64-byte boundaries. If they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set. If this occurs send a SIGBUS to the offending process if in user mode. If in kernel mode call bad_page_fault(). Signed-off-by: Jordan Niethe --- v2

[PATCH v3 04/14] powerpc sstep: Add support for prefixed load/stores

2020-02-25 Thread Jordan Niethe
-Precision (plxssp) * Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1) * Prefixed Store VSX Scalar Doubleword (pstxsd) * Prefixed Store VSX Scalar Single-Precision (pstxssp) * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1) Signed-off-by: Jordan Niethe --- v2: - Combine all load/store

[PATCH v3 03/14] powerpc sstep: Prepare to support prefixed instructions

2020-02-25 Thread Jordan Niethe
are emulated or analysed - this is just making it possible to do so. Signed-off-by: Jordan Niethe --- v2: - Move definition of __get_user_instr() and __get_user_instr_inatomic() to "powerpc: Support prefixed instructions in alignment handler." - Use a macro for returning the length of an op

[PATCH v3 14/14] powerpc: Add prefix support to mce_find_instr_ea_and_pfn()

2020-02-25 Thread Jordan Niethe
mce_find_instr_ea_and_pfn analyses an instruction to determine the effective address that caused the machine check. Update this to load and pass the suffix to analyse_instr for prefixed instructions. Signed-off-by: Jordan Niethe --- v2: - Rename sufx to suffix --- arch/powerpc/kernel

Re: [PATCH v3 07/14] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception()

2020-02-26 Thread Jordan Niethe
pare for dealing with emulated prefixed instructions by checking > > for this bit. > > > > Signed-off-by: Jordan Niethe > > Oh you've got it here, I would just squash this together with the first > patch. Sure, I'll put them together. When you mentioned a couple more

Re: [PATCH v3 11/14] powerpc/kprobes: Support kprobes on prefixed instructions

2020-02-27 Thread Jordan Niethe
On Fri, Feb 28, 2020 at 12:48 PM Nicholas Piggin wrote: > > Jordan Niethe's on February 27, 2020 10:58 am: > > On Wed, Feb 26, 2020 at 6:18 PM Nicholas Piggin wrote: > >> > >> Jordan Niethe's on February 26, 2020 2:07 pm: > >> > @@ -136,11 +148,14 @@ int arch_prepare_kprobe(struct kprobe *p) >

Re: [PATCH v3 01/14] powerpc: Enable Prefixed Instructions

2020-02-27 Thread Jordan Niethe
On Wed, Feb 26, 2020 at 5:50 PM Nicholas Piggin wrote: > > Jordan Niethe's on February 26, 2020 2:07 pm: > > From: Alistair Popple > > > > Prefix instructions have their own FSCR bit which needs to enabled via > > a CPU feature. The kernel will save the FSCR for problem state but it > > needs to

Re: [PATCH v3 09/14] powerpc/xmon: Add initial support for prefixed instructions

2020-02-26 Thread Jordan Niethe
; Adding prefixed instructions complicates this as the bpt::instr[1] needs > > to be used to hold the suffix. To deal with this make bpt::instr[] big > > enough for three word instructions. bpt::instr[2] contains the trap, > > and in the case of word instructions pad bpt::instr[1]

Re: [PATCH v3 08/14] powerpc/xmon: Remove store_inst() for patch_instruction()

2020-02-26 Thread Jordan Niethe
to xmon. In some places patch_instruction() is already > > being using followed by store_inst(). In these cases just remove the > > store_inst(). Otherwise replace store_inst() with patch_instruction(). > > > > Signed-off-by: Jordan Niethe > > --- > > arch/p

Re: [PATCH v3 11/14] powerpc/kprobes: Support kprobes on prefixed instructions

2020-02-26 Thread Jordan Niethe
On Wed, Feb 26, 2020 at 6:18 PM Nicholas Piggin wrote: > > Jordan Niethe's on February 26, 2020 2:07 pm: > > @@ -136,11 +148,14 @@ int arch_prepare_kprobe(struct kprobe *p) > > } > > > > if (!ret) { > > - patch_instruction(p->ainsn.insn, *p->addr); > > +

Re: [PATCH v3 09/14] powerpc/xmon: Add initial support for prefixed instructions

2020-02-27 Thread Jordan Niethe
On Thu, Feb 27, 2020 at 6:14 PM Christophe Leroy wrote: > > > > Le 27/02/2020 à 01:11, Jordan Niethe a écrit : > > On Wed, Feb 26, 2020 at 6:10 PM Nicholas Piggin wrote: > >> > >> Jordan Niethe's on February 26, 2020 2:07 pm: > >>> A prefixed ins

Re: [PATCH 06/18] powerpc sstep: Add support for prefixed integer load/stores

2020-02-06 Thread Jordan Niethe
On Fri, Jan 10, 2020 at 9:38 PM Balamuruhan S wrote: > > On Tue, Nov 26, 2019 at 04:21:29PM +1100, Jordan Niethe wrote: > > This adds emulation support for the following prefixed integer > > load/stores: > > * Prefixed Load Byte and Zero (plbz) > > * Prefixe

Re: [PATCH 06/18] powerpc sstep: Add support for prefixed integer load/stores

2020-02-06 Thread Jordan Niethe
On Sat, Jan 11, 2020 at 2:13 AM Balamuruhan S wrote: > > On Tue, Nov 26, 2019 at 04:21:29PM +1100, Jordan Niethe wrote: > > This adds emulation support for the following prefixed integer > > load/stores: > > * Prefixed Load Byte and Zero (plbz) > > * Prefixe

Re: [PATCH 15/18] powerpc/uprobes: Add support for prefixed instructions

2020-02-06 Thread Jordan Niethe
On Mon, Jan 13, 2020 at 10:30 PM Balamuruhan S wrote: > > On Tue, Nov 26, 2019 at 04:21:38PM +1100, Jordan Niethe wrote: > > Uprobes can execute instructions out of line. Increase the size of the > > buffer used for this so that this works for prefixed instructions. Tak

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

2020-02-06 Thread Jordan Niethe
On Mon, Jan 13, 2020 at 5:18 PM Balamuruhan S wrote: > > On Tue, Nov 26, 2019 at 04:21:28PM +1100, Jordan Niethe wrote: > > Currently all instructions are a single word long. A future ISA version > > will include prefixed instructions which have a double word length. The

Re: [PATCH 18/18] powerpc/fault: Use analyse_instr() to check for store with updates to sp

2020-02-07 Thread Jordan Niethe
On Fri, Feb 7, 2020 at 7:16 PM Greg Kurz wrote: > > On Thu, 19 Dec 2019 01:11:33 +1100 > Daniel Axtens wrote: > > > Jordan Niethe writes: > > > > > A user-mode access to an address a long way below the stack pointer is > > > only valid if the inst

Re: [PATCH v2 03/13] powerpc sstep: Prepare to support prefixed instructions

2020-02-11 Thread Jordan Niethe
On Tue, Feb 11, 2020 at 4:57 PM Christophe Leroy wrote: > > > > Le 11/02/2020 à 06:33, Jordan Niethe a écrit : > > Currently all instructions are a single word long. A future ISA version > > will include prefixed instructions which have a double word length. The > >

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

2020-01-06 Thread Jordan Niethe
On Fri, Dec 20, 2019 at 4:17 PM Jordan Niethe wrote: > > On Thu, Dec 19, 2019 at 1:15 AM Daniel Axtens wrote: > > > > Jordan Niethe writes: > > > > > Currently all instructions are a single word long. A future ISA version > > > will include prefixed in

Re: [PATCH v5 05/21] powerpc: Use a function for getting the instruction op code

2020-04-08 Thread Jordan Niethe
On Thu, Apr 9, 2020 at 4:21 AM Segher Boessenkool wrote: > > Hi! > > On Mon, Apr 06, 2020 at 06:09:20PM +1000, Jordan Niethe wrote: > > +static inline int ppc_inst_opcode(u32 x) > > +{ > > + return x >> 26; > > +} > > Maybe you should hav

Re: [PATCH v5 13/21] powerpc/xmon: Use a function for reading instructions

2020-04-08 Thread Jordan Niethe
On Thu, Apr 9, 2020 at 3:04 PM Balamuruhan S wrote: > > On Wed, 2020-04-08 at 12:18 +1000, Jordan Niethe wrote: > > On Tue, Apr 7, 2020 at 9:31 PM Balamuruhan S wrote: > > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > > > Currently in

Re: [PATCH v5 02/21] powerpc/xmon: Move out-of-line instructions to text section

2020-04-09 Thread Jordan Niethe
On Thu, Apr 9, 2020 at 4:11 PM Christophe Leroy wrote: > > > > Le 06/04/2020 à 10:09, Jordan Niethe a écrit : > > To execute an instruction out of line after a breakpoint, the NIP is set > > to the address of struct bpt::instr. Here a copy of the instructi

Re: [PATCH v5 00/21] Initial Prefixed Instruction support

2020-04-09 Thread Jordan Niethe
On Thu, Apr 9, 2020 at 4:39 PM Christophe Leroy wrote: > > > > On 04/06/2020 08:09 AM, Jordan Niethe wrote: > > A future revision of the ISA will introduce prefixed instructions. A > > prefixed instruction is composed of a 4-byte prefix followed by a > > 4-byte suf

Re: [PATCH v5 18/21] powerpc64: Add prefixed instructions to instruction data type

2020-04-14 Thread Jordan Niethe
On Mon, Apr 13, 2020 at 10:04 PM Balamuruhan S wrote: > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > For powerpc64, redefine the ppc_inst type so both word and prefixed > > instructions can be represented. On powerpc32 the type will remain the > > same.

Re: [PATCH v5 09/21] powerpc: Use a datatype for instructions

2020-04-07 Thread Jordan Niethe
On Tue, Apr 7, 2020 at 8:30 PM Balamuruhan S wrote: > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > Currently unsigned ints are used to represent instructions on powerpc. > > This has worked well as instructions have always been 4 byte words. > > Howev

Re: [PATCH v5 13/21] powerpc/xmon: Use a function for reading instructions

2020-04-07 Thread Jordan Niethe
On Tue, Apr 7, 2020 at 9:31 PM Balamuruhan S wrote: > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > Currently in xmon, mread() is used for reading instructions. In > > preparation for prefixed instructions, create and use a new function, > > mread_instr()

Re: [PATCH v5 12/21] powerpc: Introduce a function for reporting instruction length

2020-04-07 Thread Jordan Niethe
On Tue, Apr 7, 2020 at 9:15 PM Balamuruhan S wrote: > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > Currently all instructions have the same length, but in preparation for > > prefixed instructions introduce a function for returning instruction > > le

Re: [PATCH v5 11/21] powerpc: Define and use __get_user_instr{, inatomic}()

2020-04-07 Thread Jordan Niethe
On Tue, Apr 7, 2020 at 8:48 PM Balamuruhan S wrote: > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > Define specific __get_user_instr() and __get_user_instr_inatomic() > > macros for reading instructions from user space. > > > > Signed-off-by: Jo

Re: [PATCH v5 03/21] powerpc: Change calling convention for create_branch() et. al.

2020-04-07 Thread Jordan Niethe
On Tue, Apr 7, 2020 at 4:10 PM Balamuruhan S wrote: > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > create_branch(), create_cond_branch() and translate_branch() return the > > instruction that they create, or return 0 to signal an error. Seperate > > s/

Re: [PATCH v5 05/21] powerpc: Use a function for getting the instruction op code

2020-04-06 Thread Jordan Niethe
On Mon, Apr 6, 2020 at 6:22 PM Christophe Leroy wrote: > > > > Le 06/04/2020 à 10:09, Jordan Niethe a écrit : > > In preparation for using a data type for instructions that can not be > > directly used with the '>>' operator use a function for getting the

Re: [PATCH v5 04/21] powerpc: Use a macro for creating instructions from u32s

2020-04-07 Thread Jordan Niethe
On Tue, Apr 7, 2020 at 4:40 PM Balamuruhan S wrote: > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > In preparation for instructions having a more complex data type start > > using a macro, ppc_inst(), for making an instruction out of a u32. A &g

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