don't have any reasonable other
possibility to stuff things into this field, I think it would make sense
to do the cleanup the other way around: keep the irq_set_chip_data
arch_setup_msi_irq() and rip it out of the individual drivers.
Regards,
Lucas
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. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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other platform MSI
arch code to eliminate weak arch MSI functions. This patch add
.restore_irq() and .setup_irqs() to make it become more common.
Signed-off-by: Yijing Wang wangyij...@huawei.com
This change looks good to me:
Reviewed-by: Lucas Stach l.st...@pengutronix.de
---
drivers/pci
Am Freitag, den 05.09.2014, 18:10 +0800 schrieb Yijing Wang:
Now we use struct msi_chip in all platforms to configure
MSI/MSI-X. We can clean up the unused arch functions.
Signed-off-by: Yijing Wang wangyij...@huawei.com
Reviewed-by: Lucas Stach l.st...@pengutronix.de
---
drivers/iommu
Am Dienstag, den 16.09.2014, 09:30 +0800 schrieb Yijing Wang:
On 2014/9/15 22:00, Lucas Stach wrote:
Am Freitag, den 05.09.2014, 18:09 +0800 schrieb Yijing Wang:
Currently, pcie-designware, pcie-rcar, pci-tegra drivers
use irq chip_data to save the msi_chip pointer. They
already call
() in the 3.18 cycle
and I would think it would be no problem to to the same with rcar.
Regards,
Lucas
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{
+compatible = fsl,sgtl5000;
+reg = 0x0a;
+clocks = clks VF610_CLK_SAI2;
+ };
+};
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim
Hi,
Am Freitag, den 28.09.2018, 12:43 -0700 schrieb Frank Rowand:
> + Frank
>
> On 09/27/18 15:25, Li Yang wrote:
> > Hi Rob and Grant,
> >
> > Various device tree specs are recommending to include all the
> > potential compatible strings in the device node, with the order from
> > most
Am Montag, den 22.07.2019, 15:48 +0300 schrieb Daniel Baluta:
> FIFO combining mode allows the separate FIFOs for multiple data
> channels
> to be used as a single FIFO for either software accesses or a single
> data
> channel or both.
>
> FIFO combined mode is described in chapter 13.10.3.5.4
Am Montag, den 22.07.2019, 15:48 +0300 schrieb Daniel Baluta:
> SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM)
> at the beginning of register address space.
>
> On imx7ulp FIFOs can held up to 16 x 32 bit samples.
> On imx8mq FIFOs can held up to 128 x 32 bit samples.
>
>
Am Montag, den 22.07.2019, 15:48 +0300 schrieb Daniel Baluta:
> SAI supports up to 8 Rx/Tx data lines which can be enabled
> using TCE/RCE bits of TCR3/RCR3 registers.
>
> Data lines to be enabled are read from DT fsl,dl_mask property.
> By default (if no DT entry is provided) only data line 0 is
Am Montag, den 22.07.2019, 15:48 +0300 schrieb Daniel Baluta:
> SAI supports up to 8 data lines. This property let the user
> configure how many data lines should be used per transfer
> direction (Tx/Rx).
>
> > Signed-off-by: Daniel Baluta
> ---
>
Am Dienstag, den 19.05.2020, 17:41 +0800 schrieb Shengjiu Wang:
> There are two requirements that we need to move the request
> of dma channel from probe to open.
How do you handle -EPROBE_DEFER return code from the channel request if
you don't do it in probe?
> - When dma device binds with
Am Mittwoch, den 20.05.2020, 16:20 +0800 schrieb Shengjiu Wang:
> Hi
>
> On Tue, May 19, 2020 at 6:04 PM Lucas Stach wrote:
> > Am Dienstag, den 19.05.2020, 17:41 +0800 schrieb Shengjiu Wang:
> > > There are two requirements that we need to move the request
> &g
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