Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index
time, talitos
driver shall support both SEC1 and SEC2+ at the same time.
Based on cryptodev-2.6 tree
Christophe Leroy (17):
crypto: talitos - Use zero entry to init descriptors ptrs to zero
crypto: talitos - Refactor the sg in/out chain allocation
crypto: talitos - talitos_ptr renamed ptr
Linux CodyingStyle recommends to use short variables for local
variables. ptr is just good enough for those 3 lines functions.
It helps keep single lines shorter than 80 characters.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 20 ++--
1 file changed, 10
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 159 ---
1 file changed, 81 insertions(+), 78 deletions(-)
diff --git a/drivers
This patch adds a helper function for reads and writes of the len
param of the talitos descriptor. This will help implement
SEC1 later.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a
map_single_talitos_ptr() is always called with extent == 0, so lets remove this
unused parameter
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b
This patch enhances the talitos_desc struct with fields for SEC1.
SEC1 has only one header field, and has a 'next_desc' field in
addition.
This mixed descriptor will continue to fit SEC2, and for SEC1
we will recopy hdr value into hdr1 value in talitos_submit()
Signed-off-by: Christ
This patch adds a CONFIG option to select SEC1, SEC2+ or both.
Signed-off-by: Christophe Leroy
---
drivers/crypto/Kconfig | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 800bf41..8a76a01 100644
--- a/drivers/crypto
value. If both are compiled in, feature
field is checked.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos.h | 17 +
2 files changed, 20 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index bca6ded..db95
talitos descriptor is slightly different for SEC1 and SEC2+, so
lets the helper function that fills the descriptor take into account
the type of SEC.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 105 ++-
1 file changed, 67 insertions
SEC1 descriptor is a bit different to SEC2+ descriptor.
talitos_submit() will have to copy hdr field into hdr1 field and
send the descriptor starting at hdr1 up to next_desc.
For SEC2, it remains unchanged and next_desc is just ignored.
Signed-off-by: Christophe Leroy
---
drivers/crypto
SEC 1.0, 1.2 and 2.x+ have different EU base addresses, so we need to
define pointers for each EU in the driver private data structure.
The proper address is set by the probe function depending on the
SEC type, in order to provide access to the proper address.
Signed-off-by: Christophe Leroy
SEC1.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 227 +++
drivers/crypto/talitos.h | 39 +---
2 files changed, 199 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6d77699
iptors
We also adapt the max buffer size which is only 32k on SEC1 while it
is 64k on SEC2+
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 138 ++-
drivers/crypto/talitos.h | 3 +-
2 files changed, 103 insertions(+), 38 deletions(-)
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index dddf4b3
We add a specific compatible for SEC1, to handle the differences
between SEC1 and SEC2+
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index f1406d7b..c04074d 100644
This patch updates the documentation by including SEC1 into SEC2/3 doc
Signed-off-by: Christophe Leroy
---
Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
b
time, talitos
driver shall support both SEC1 and SEC2+ at the same time.
Based on cryptodev-2.6 tree
Christophe Leroy (17):
crypto: talitos - Use zero entry to init descriptors ptrs to zero
crypto: talitos - Refactor the sg in/out chain allocation
crypto: talitos - talitos_ptr renamed ptr
Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 159 ---
1 file changed, 81 insertions(+), 78 deletions(-)
diff --git a/drivers
Linux CodyingStyle recommends to use short variables for local
variables. ptr is just good enough for those 3 lines functions.
It helps keep single lines shorter than 80 characters.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 20 ++--
1 file changed, 10
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b
map_single_talitos_ptr() is always called with extent == 0, so lets remove this
unused parameter
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto
This patch adds a helper function for reads and writes of the len
param of the talitos descriptor. This will help implement
SEC1 later.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a
This patch enhances the talitos_desc struct with fields for SEC1.
SEC1 has only one header field, and has a 'next_desc' field in
addition.
This mixed descriptor will continue to fit SEC2, and for SEC1
we will recopy hdr value into hdr1 value in talitos_submit()
Signed-off-by: Christ
This patch adds a CONFIG option to select SEC1, SEC2+ or both.
Signed-off-by: Christophe Leroy
---
drivers/crypto/Kconfig | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 800bf41..8a76a01 100644
--- a/drivers/crypto
value. If both are compiled in, feature
field is checked.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos.h | 17 +
2 files changed, 20 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index bca6ded..db95
talitos descriptor is slightly different for SEC1 and SEC2+, so
lets the helper function that fills the descriptor take into account
the type of SEC.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 105 ++-
1 file changed, 67 insertions
SEC1 descriptor is a bit different to SEC2+ descriptor.
talitos_submit() will have to copy hdr field into hdr1 field and
send the descriptor starting at hdr1 up to next_desc.
For SEC2, it remains unchanged and next_desc is just ignored.
Signed-off-by: Christophe Leroy
---
drivers/crypto
SEC 1.0, 1.2 and 2.x+ have different EU base addresses, so we need to
define pointers for each EU in the driver private data structure.
The proper address is set by the probe function depending on the
SEC type, in order to provide access to the proper address.
Signed-off-by: Christophe Leroy
SEC1.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 227 +++
drivers/crypto/talitos.h | 39 +---
2 files changed, 199 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6d77699
iptors
We also adapt the max buffer size which is only 32k on SEC1 while it
is 64k on SEC2+
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 138 ++-
drivers/crypto/talitos.h | 3 +-
2 files changed, 103 insertions(+), 38 deletions(-)
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index dddf4b3
We add a specific compatible for SEC1, to handle the differences
between SEC1 and SEC2+
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index f1406d7b..c04074d 100644
This patch updates the documentation by including SEC1 into SEC2/3 doc
Signed-off-by: Christophe Leroy
---
Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
b
mmu_virtual_psize shall be set to MMU_PAGE_16K when 16k pages have
been selected
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu-8xx.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mmu-8xx.h
b/arch/powerpc/include/asm/mmu-8xx.h
index
11 - powerpc/8xx: Add support for TASK_SIZE greater than 0x8000
All changes have been successfully tested on MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
arch/powerpc/include/asm/page.h | 8 +++
arch/powerpc/include/asm/pgtable-ppc32.h | 37
Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk"), MD_EPN and
MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 6 --
1 file changed, 6 deletions(-)
diff --git
tries, remove all those
tests and let the 8xx handle it. This reduce the number of cycle when the
entries are valid which is the case most of the time, and doesn't significantly
increase the time for handling invalid entries.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_
When pages are not 4K, PGDIR table is allocated with kmalloc(). In order to
optimise TLB handlers, aligned memory is needed. kmalloc() doesn't provide
aligned memory blocks, so lets use a kmem_cache pool instead.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable-ppc32.h
L1 base address is now aligned so we can insert L1 index into r11 directly and
then preserve r10
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 34 +++---
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/kernel
All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 22 ++
1 file changed, 10 insertions(+), 12 deletions
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index aa45225..b227902e 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b227902e..b3f3cb5 100644
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel
e for saving CR
- Otherwise, we use r10, then we reload SRR0/MD_EPN into r10 when CR is restored
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 53 +-
1 file changed, 37 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/k
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29
This patchset provides a further optimisation of TLB handling in the 8xx.
Changes are:
- Not saving registers like CR when not needed
- Adding support to any TASK_SIZE
Only the last patch of the set is changed compared to v4
Resending with proper From: this time.
Christophe Leroy (5):
powerpc
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 9b53fe1..1279018 100644
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel
en CR is restored
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 5a69c5e..150d03f 100644
--- a/arch/powerpc/k
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a
most of the time it is equal to 0xC000
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index ba2dc53..c640bbb
All kernel pages have to be marked as shared in order to not perform
CASID verification.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pte-8xx.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/pte-8xx.h
b/arch/powerpc/include
erformed as supervisor
according to page definition)
This removes the special 8xx handling in pte_update()
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable-ppc32.h | 19 ---
arch/powerpc/include/asm/pte-8xx.h | 27 +-
User, exec => 01 (rights according to page definition)
GP3 (11) => User, exec => 00 (all accesses performed as supervisor)
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/cputable.h | 2 +-
arch/powerpc/include/asm/mmu-8xx.h | 26 ++
arch/powerpc/i
This patchset implements execute protection on the 8xx.
It also simplifies the handling of PAGE_USER and PAGE_RO,
and adds a small fix to the kernel pages definition.
This patchset goes on to of my previous patchset named
"[v5] powerpc8xx: Further optimisation of TLB handling"
Christ
e
CPM UART: when the CPM is of type CPM1, we simply do an of_iomap() of
the area provided via the device tree.
Signed-off-by: Christophe Leroy
---
v2: Use devm_ioremap_resource() instead of_iomap()
drivers/spi/spi-fsl-cpm.c | 35 ++-
1 file changed, 18 inser
r the same principle as for the
CPM UART: when the CPM is of type CPM1, we simply do an
devm_ioremap_resource() of the area provided via the device tree.
Signed-off-by: Christophe Leroy
---
v2: Use devm_ioremap_resource() instead of_iomap()
v3: Replaced of_iomap() by devm_ioremap_resource() in the
devm_ioremap_resource() doesn't return NULL but an ERR_PTR on error.
Reported-by: Jonas Gorsky
Signed-off-by: Christophe Leroy
---
drivers/spi/spi-fsl-cpm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c
Le 25/03/2015 02:22, Scott Wood a écrit :
On Tue, Feb 03, 2015 at 12:39:27PM +0100, LEROY Christophe wrote:
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/checksum_32.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/lib/checksum_32.S b
Le 25/03/2015 03:10, Scott Wood a écrit :
On Tue, 2015-02-03 at 12:39 +0100, Christophe Leroy wrote:
csum_tcpudp_magic() is only a few instructions, and does not modifies any other
register than the returned result. So it is not worth having it as a separate
function and suffer function
Le 25/03/2015 02:30, Scott Wood a écrit :
On Tue, Feb 03, 2015 at 12:39:27PM +0100, LEROY Christophe wrote:
The C version of csum_add() as defined in include/net/checksum.h gives the
following assembly:
0: 7c 04 1a 14 add r0,r4,r3
4: 7c 64 00 10 subfc
This patchset implements use of cacheable versions of memset and
memcpy when the len is greater than the cacheline size and the
destination is in RAM.
On MPC885, we observe a 7% rate increase on FTP transfer
Christophe Leroy (4):
Partially revert "powerpc: Remove duplicate cacheable_m
heline with the data that we will overwrite.
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 127 +
1 file changed, 127 insertions(+)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index 6813f80..55f19f9 100644
--
We swap r4 and r5, this avoids having to move the len contained in r4
into r5
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32
back to
generic_memcpy()
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index cbca76c..d8a9a86 100644
--- a/arch/powerpc/lib/copy_32.S
+++ b
, we get approximatly 7% increase of the transfer rate
on an FTP reception
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index
Le 14/05/2015 02:55, Scott Wood a écrit :
On Tue, 2015-05-12 at 15:32 +0200, Christophe Leroy wrote:
cacheable_memzero uses dcbz instruction and is more efficient than
memset(0) when the destination is in RAM
This patch renames memset as generic_memset, and defines memset
as a prolog to
Le 14/05/2015 02:49, Scott Wood a écrit :
On Tue, 2015-05-12 at 15:32 +0200, Christophe Leroy wrote:
This partially reverts
commit 'powerpc: Remove duplicate cacheable_memcpy/memzero functions
("f909a35bdfb7cb350d078a2cf888162eeb20381c")'
I don't ha
This patchset implements use of cacheable versions of memset and
memcpy since when the destination is not cacheable, memset_io
and memcpy_toio are used.
On MPC885, we observe a 7% rate increase on FTP transfer
Christophe Leroy (6):
powerpc: use memset_io() to clear CPM Muram
Partially revert
CPM muram is not cached, so use memset_io() instead of memset()
Signed-off-by: Christophe Leroy
---
arch/powerpc/sysdev/cpm_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index 4f78695..e2ea519
heline with the data that we will overwrite.
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 127 +
1 file changed, 127 insertions(+)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index 6813f80..55f19f9 100644
--
()
cacheable_memzero disappears as it is not referenced anywhere anymore
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index 55f19f9..0b4f954 100644
--- a
cacheable_memzero() which has become the new memset() and the old
memset() are quite similar, so just merge them.
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 34 +++---
1 file changed, 7 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc
approximatly 7% increase of the transfer rate
on an FTP reception
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index 9262071..1d49c74 100644
--- a
This patch adds a few optimisations in memcpy functions by using
lbzu/stbu instead of lxb/stb and by re-ordering insn inside a loop
to reduce latency due to loading
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/copy_32.S | 10 +-
1 file changed, 5 insertions(+), 5 deletions
This patchset provides a few optimisations related to IP checksum functions.
Christophe Leroy (2):
powerpc: put csum_tcpudp_magic inline
powerpc: add support for csum_add()
arch/powerpc/include/asm/checksum.h | 37 -
arch/powerpc/lib/checksum_32.S
.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/checksum.h | 21 -
arch/powerpc/lib/checksum_32.S | 16
arch/powerpc/lib/checksum_64.S | 21 -
3 files changed, 12 insertions(+), 46 deletions(-)
diff --git a/arch/powerpc
r3,r4,r3
0xc0001b0c <+20>:clrldi r3,r3,32
0xc0001b10 <+24>:blr
include/net/checksum.h also offers the possibility to define an arch specific
function.
This patch provides a specific csum_add() inline function.
Signed-off-by: Christophe Leroy
---
implementing a 16 bit alignment of
the
PGDIR. It is not worth potentially wasting up to 64k of memory just for
removing one
instruction (ori).
2) I managed to preserve r11 while calculating the level 2 address, therefore
no more need to save r11 into CR.
Signed-off-by: Christophe Leroy
Tested
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h |3 ++-
arch
-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 104 --
1 files changed, 36 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1329c5a..3af6db1 100644
--- a/arch/powerpc/kernel
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 17 +++--
1 files changed, 7 insertions(+), 10
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |8 ++--
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |7 +++
1 files changed, 3 insertions(+), 4 deletions
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S |4
3 files changed, 7 insertions(+), 1 deletions(-)
diff
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |8 +---
1 files changed, 5 insertions(+), 3
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable-ppc32.h | 21 +
arch/powerpc/include/asm/pte-8xx.h |7 +--
arch/powerpc/kernel/head_8xx.S |
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 28
1 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/kernel
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 23 ++-
1 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/arch
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 30 ++
1 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/arch
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 19
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