[PATCH 4/15] bootwrapper: smp support code
Support code to move cpus around, both a spin loop and c code to move the cpus before uncompressing and copying the kernel to 0. The low level code is designed to be included in a crt0 or other assembly file because it may need to be at a fixed location or there may be other entry point requirements. Note: this code works with kernel head_64.S. head_6xx.S needs the 0x60 entry point (it currently mentions something at address 0xC0; but the similar code is at 0xC4); the other heads don't appear to support SMP. Signed-off-by: Milton Miller [EMAIL PROTECTED] --- vs 12171 get barrier from io.h instead of adding to reg.h rediff ops.h, Makefile Index: kernel/arch/powerpc/boot/marshal_low.S === --- /dev/null 1970-01-01 00:00:00.0 + +++ kernel/arch/powerpc/boot/marshal_low.S 2007-09-17 22:13:14.0 -0500 @@ -0,0 +1,103 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright 2007 IBM Corporation. + * + * Authors: Milton Miller [EMAIL PROTECTED] + * + */ + +#include ppc_asm.h + + .text + /* +* This code is designed to be a kexec entry point block. +* That is, it has both code for the master cpu that begins +* at offset 0 as linked into the image, and a sequence of +* 0x100 bytes that, when copied to address 0, forms the +* wait loop for slave cpus. Each slave should have its +* unique hardware cpu identifier in r3 before entering +* this code. +*/ + .globl master +master: b _zimage_start_plat + + .global slave_wait +slave_wait: + /* r3 cpu id, r4 slaves_wait, r5 cpu bit, r6 cpu mask word offset */ + + /* set our bit in the slaves mask */ +98:lwarx r7,r4,r6 + or r8,r7,r5 + stwcx. r8,r4,r6 + bne 98b + + and.r8,r7,r5 + bnel- err_slave + +99:lwz r7,gohere-slave_wait(r4) + cmpwi 0,r7,0 + beq 99b + mtctr r7 + mr r4,r7 + bctr + + + .global gohere +gohere:.long 0 /* when set the slave moves */ + + +err_slave: + stw r5,slave_error-slave_wait(4)/* no locking */ + blr + + .globl slave_error /* set when slave detects error */ +slave_error: + .long 0 + + /* +* The slaves may be in 32 or 64 bit mode, we don't care +* r3 is the slave cpu number, matching the device tree. +*/ + .orgmaster+0x60 + .globl slave +slave: bl 1f +1: mflrr4 + addir4,r4,slave_wait-1b /* code assumes r4=slave_wait */ + li r5,1 + rlwnm r5,r5,r3,0,31 /* bit within word */ + rlwinm r6,r3,32-5+2,4,29 /* word in array */ + addir6,r6,slaves-slave_wait /* relative to r4, slave_wait */ + b slave_wait + + .orgmaster+0x80 /* put locked bitmask data in another line */ + .global slaves +slaves: + + .globl slaves_end; +slaves_end = 0f + +#if 0 + /* today, the 32 bit kernel starts slaves at 0xc0 +* but this limits us to cpu to 512 vs 1024 +*/ + .orgmaster+0xc0 +0: b slave +#endif + + + .orgmaster+0x100/* we must fit in 0x100 bytes */ +0: + Index: kernel/arch/powerpc/boot/marshal.c === --- /dev/null 1970-01-01 00:00:00.0 + +++ kernel/arch/powerpc/boot/marshal.c 2007-09-17 22:13:14.0 -0500 @@ -0,0 +1,276 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor,
[PATCH 4/15] bootwrapper: smp support code
Support code to move cpus around, both a spin loop and c code to move the cpus before uncompressing and copying the kernel to 0. The low level code is designed to be included in a crt0 or other assembly file because it may need to be at a fixed location or there may be other entry point requirements. Note: this code works with kernel head_64.S. head_6xx.S needs the 0x60 entry point (it currently uses something closer to 0xC0; but the similar code is at 0xC4); the other heads don't appear to support SMP. Signed-off-by: Milton Miller [EMAIL PROTECTED] --- Cleaned up documentation. Hopefully the format is correct. Removed the #if 1 #else #endif Move hidden asm code outside function instead of branching over it. This code has previously survied days of kexec stress and also works when the next stage is itself (ie zBoot to zImage). Index: work.git/arch/powerpc/boot/marshal_low.S === --- /dev/null 1970-01-01 00:00:00.0 + +++ work.git/arch/powerpc/boot/marshal_low.S2007-07-10 03:48:20.0 -0500 @@ -0,0 +1,103 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright 2007 IBM Corporation. + * + * Authors: Milton Miller [EMAIL PROTECTED] + * + */ + +#include ppc_asm.h + + .text + /* +* This code is designed to be a kexec entry point block. +* That is, it has both code for the master cpu that begins +* at offset 0 as linked into the image, and a sequence of +* 0x100 bytes that, when copied to address 0, forms the +* wait loop for slave cpus. Each slave should have its +* unique hardware cpu identifier in r3 before entering +* this code. +*/ + .globl master +master: b _zimage_start_plat + + .global slave_wait +slave_wait: + /* r3 cpu id, r4 slaves_wait, r5 cpu bit, r6 cpu mask word offset */ + + /* set our bit in the slaves mask */ +98:lwarx r7,r4,r6 + or r8,r7,r5 + stwcx. r8,r4,r6 + bne 98b + + and.r8,r7,r5 + bnel- err_slave + +99:lwz r7,gohere-slave_wait(r4) + cmpwi 0,r7,0 + beq 99b + mtctr r7 + mr r4,r7 + bctr + + + .global gohere +gohere:.long 0 /* when set the slave moves */ + + +err_slave: + stw r5,slave_error-slave_wait(4)/* no locking */ + blr + + .globl slave_error /* set when slave detects error */ +slave_error: + .long 0 + + /* +* The slaves may be in 32 or 64 bit mode, we don't care +* r3 is the slave cpu number, matching the device tree. +*/ + .orgmaster+0x60 + .globl slave +slave: bl 1f +1: mflrr4 + addir4,r4,slave_wait-1b /* code assumes r4=slave_wait */ + li r5,1 + rlwnm r5,r5,r3,0,31 /* bit within word */ + rlwinm r6,r3,32-5+2,4,29 /* word in array */ + addir6,r6,slaves-slave_wait /* relative to r4, slave_wait */ + b slave_wait + + .orgmaster+0x80 /* put locked bitmask data in another line */ + .global slaves +slaves: + + .globl slaves_end; +slaves_end = 0f + +#if 0 + /* today, the 32 bit kernel starts slaves at 0xc0 +* but this limits us to cpu to 512 vs 1024 +*/ + .orgmaster+0xc0 +0: b slave +#endif + + + .orgmaster+0x100/* we must fit in 0x100 bytes */ +0: + Index: work.git/arch/powerpc/boot/marshal.c === --- /dev/null 1970-01-01 00:00:00.0 + +++ work.git/arch/powerpc/boot/marshal.c2007-07-10 03:48:20.0 -0500 @@ -0,0 +1,275 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public
