Re: [PATCH v2 2/8] powerpc/xive: guest exploitation of the XIVE interrupt controller
On Fri, Aug 11, 2017 at 04:23:35PM +0200, Cédric Le Goater wrote:
> This is the framework for using XIVE in a PowerVM guest. The support
> is very similar to the native one in a much simpler form.
>
> Instead of OPAL calls, a set of Hypervisors call are used to configure
> the interrupt sources and the event/notification queues of the guest:
>
> - H_INT_GET_SOURCE_INFO
>
>used to obtain the address of the MMIO page of the Event State
>Buffer (PQ bits) entry associated with the source.
>
> - H_INT_SET_SOURCE_CONFIG
>
>assigns a source to a "target".
>
> - H_INT_GET_SOURCE_CONFIG
>
>determines to which "target" and "priority" is assigned to a source
>
> - H_INT_GET_QUEUE_INFO
>
>returns the address of the notification management page associated
>with the specified "target" and "priority".
>
> - H_INT_SET_QUEUE_CONFIG
>
>sets or resets the event queue for a given "target" and "priority".
>It is also used to set the notification config associated with the
>queue, only unconditional notification for the moment. Reset is
>performed with a queue size of 0 and queueing is disabled in that
>case.
>
> - H_INT_GET_QUEUE_CONFIG
>
>returns the queue settings for a given "target" and "priority".
>
> - H_INT_RESET
>
>resets all of the partition's interrupt exploitation structures to
>their initial state, losing all configuration set via the hcalls
>H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
>
> - H_INT_SYNC
>
>issue a synchronisation on a source to make sure sure all
>notifications have reached their queue.
>
> As for XICS, the XIVE interface for the guest is described in the
> device tree under the "interrupt-controller" node. A couple of new
> properties are specific to XIVE :
>
> - "reg"
>
>contains the base address and size of the thread interrupt
>managnement areas (TIMA) for the user level for the OS level. Only
>the OS level is taken into account.
>
> - "ibm,xive-eq-sizes"
>
>the size of the event queues.
>
> - "ibm,xive-lisn-ranges"
>
>the interrupt numbers ranges assigned to the guest. These are
>allocated using a simple bitmap.
>
> and also :
>
> - "/ibm,plat-res-int-priorities"
>
>contains a list of priorities that the hypervisor has reserved for
>its own use.
>
> Tested with a QEMU XIVE model for pseries and with the Power
> hypervisor
>
> Signed-off-by: Cédric Le Goater
> ---
>
> Changes since v1 :
>
> - added a xive_teardown_cpu() routine
> - removed P9 doorbell support when xive is enabled.
> - merged in patch for "ibm,plat-res-int-priorities" support
> - added some comments on the usage of raw I/O accessors.
>
> Changes since RFC :
>
> - renamed backend to spapr
> - fixed hotplug support
> - fixed kexec support
> - fixed src_chip value (XIVE_INVALID_CHIP_ID)
> - added doorbell support
> - added some hcall debug logs
>
> arch/powerpc/include/asm/hvcall.h| 13 +-
> arch/powerpc/include/asm/xive.h | 3 +
> arch/powerpc/platforms/pseries/Kconfig | 1 +
> arch/powerpc/platforms/pseries/hotplug-cpu.c | 11 +-
> arch/powerpc/platforms/pseries/kexec.c | 6 +-
> arch/powerpc/platforms/pseries/setup.c | 8 +-
> arch/powerpc/platforms/pseries/smp.c | 27 +-
> arch/powerpc/sysdev/xive/Kconfig | 5 +
> arch/powerpc/sysdev/xive/Makefile| 1 +
> arch/powerpc/sysdev/xive/common.c| 13 +
> arch/powerpc/sysdev/xive/spapr.c | 617
> +++
> 11 files changed, 697 insertions(+), 8 deletions(-)
> create mode 100644 arch/powerpc/sysdev/xive/spapr.c
>
> diff --git a/arch/powerpc/include/asm/hvcall.h
> b/arch/powerpc/include/asm/hvcall.h
> index 57d38b504ff7..3d34dc0869f6 100644
> --- a/arch/powerpc/include/asm/hvcall.h
> +++ b/arch/powerpc/include/asm/hvcall.h
> @@ -280,7 +280,18 @@
> #define H_RESIZE_HPT_COMMIT 0x370
> #define H_REGISTER_PROC_TBL 0x37C
> #define H_SIGNAL_SYS_RESET 0x380
> -#define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET
> +#define H_INT_GET_SOURCE_INFO 0x3A8
> +#define H_INT_SET_SOURCE_CONFIG 0x3AC
> +#define H_INT_GET_SOURCE_CONFIG 0x3B0
> +#define H_INT_GET_QUEUE_INFO0x3B4
> +#define H_INT_SET_QUEUE_CONFIG 0x3B8
> +#define H_INT_GET_QUEUE_CONFIG 0x3BC
> +#define H_INT_SET_OS_REPORTING_LINE 0x3C0
> +#define H_INT_GET_OS_REPORTING_LINE 0x3C4
> +#define H_INT_ESB 0x3C8
> +#define H_INT_SYNC 0x3CC
> +#define H_INT_RESET 0x3D0
> +#define MAX_HCALL_OPCODE H_INT_RESET
>
> /* H_VIOCTL functions */
> #define H_GET_VIOA_DUMP_SIZE 0x01
> diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
> index c23ff4389ca2..473f133a8555 100644
> --- a/arch/powerpc/include/asm/xive.h
> +++ b/arch/powerpc/include/asm/xive.h
> @@ -110,11 +110,13 @@ extern bool __xive_enabled;
>
> static inline bool xive_enabled(void) { return __xive_enable
[PATCH v2 2/8] powerpc/xive: guest exploitation of the XIVE interrupt controller
This is the framework for using XIVE in a PowerVM guest. The support
is very similar to the native one in a much simpler form.
Instead of OPAL calls, a set of Hypervisors call are used to configure
the interrupt sources and the event/notification queues of the guest:
- H_INT_GET_SOURCE_INFO
used to obtain the address of the MMIO page of the Event State
Buffer (PQ bits) entry associated with the source.
- H_INT_SET_SOURCE_CONFIG
assigns a source to a "target".
- H_INT_GET_SOURCE_CONFIG
determines to which "target" and "priority" is assigned to a source
- H_INT_GET_QUEUE_INFO
returns the address of the notification management page associated
with the specified "target" and "priority".
- H_INT_SET_QUEUE_CONFIG
sets or resets the event queue for a given "target" and "priority".
It is also used to set the notification config associated with the
queue, only unconditional notification for the moment. Reset is
performed with a queue size of 0 and queueing is disabled in that
case.
- H_INT_GET_QUEUE_CONFIG
returns the queue settings for a given "target" and "priority".
- H_INT_RESET
resets all of the partition's interrupt exploitation structures to
their initial state, losing all configuration set via the hcalls
H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
- H_INT_SYNC
issue a synchronisation on a source to make sure sure all
notifications have reached their queue.
As for XICS, the XIVE interface for the guest is described in the
device tree under the "interrupt-controller" node. A couple of new
properties are specific to XIVE :
- "reg"
contains the base address and size of the thread interrupt
managnement areas (TIMA) for the user level for the OS level. Only
the OS level is taken into account.
- "ibm,xive-eq-sizes"
the size of the event queues.
- "ibm,xive-lisn-ranges"
the interrupt numbers ranges assigned to the guest. These are
allocated using a simple bitmap.
and also :
- "/ibm,plat-res-int-priorities"
contains a list of priorities that the hypervisor has reserved for
its own use.
Tested with a QEMU XIVE model for pseries and with the Power
hypervisor
Signed-off-by: Cédric Le Goater
---
Changes since v1 :
- added a xive_teardown_cpu() routine
- removed P9 doorbell support when xive is enabled.
- merged in patch for "ibm,plat-res-int-priorities" support
- added some comments on the usage of raw I/O accessors.
Changes since RFC :
- renamed backend to spapr
- fixed hotplug support
- fixed kexec support
- fixed src_chip value (XIVE_INVALID_CHIP_ID)
- added doorbell support
- added some hcall debug logs
arch/powerpc/include/asm/hvcall.h| 13 +-
arch/powerpc/include/asm/xive.h | 3 +
arch/powerpc/platforms/pseries/Kconfig | 1 +
arch/powerpc/platforms/pseries/hotplug-cpu.c | 11 +-
arch/powerpc/platforms/pseries/kexec.c | 6 +-
arch/powerpc/platforms/pseries/setup.c | 8 +-
arch/powerpc/platforms/pseries/smp.c | 27 +-
arch/powerpc/sysdev/xive/Kconfig | 5 +
arch/powerpc/sysdev/xive/Makefile| 1 +
arch/powerpc/sysdev/xive/common.c| 13 +
arch/powerpc/sysdev/xive/spapr.c | 617 +++
11 files changed, 697 insertions(+), 8 deletions(-)
create mode 100644 arch/powerpc/sysdev/xive/spapr.c
diff --git a/arch/powerpc/include/asm/hvcall.h
b/arch/powerpc/include/asm/hvcall.h
index 57d38b504ff7..3d34dc0869f6 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -280,7 +280,18 @@
#define H_RESIZE_HPT_COMMIT0x370
#define H_REGISTER_PROC_TBL0x37C
#define H_SIGNAL_SYS_RESET 0x380
-#define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET
+#define H_INT_GET_SOURCE_INFO 0x3A8
+#define H_INT_SET_SOURCE_CONFIG 0x3AC
+#define H_INT_GET_SOURCE_CONFIG 0x3B0
+#define H_INT_GET_QUEUE_INFO0x3B4
+#define H_INT_SET_QUEUE_CONFIG 0x3B8
+#define H_INT_GET_QUEUE_CONFIG 0x3BC
+#define H_INT_SET_OS_REPORTING_LINE 0x3C0
+#define H_INT_GET_OS_REPORTING_LINE 0x3C4
+#define H_INT_ESB 0x3C8
+#define H_INT_SYNC 0x3CC
+#define H_INT_RESET 0x3D0
+#define MAX_HCALL_OPCODE H_INT_RESET
/* H_VIOCTL functions */
#define H_GET_VIOA_DUMP_SIZE 0x01
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index c23ff4389ca2..473f133a8555 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -110,11 +110,13 @@ extern bool __xive_enabled;
static inline bool xive_enabled(void) { return __xive_enabled; }
+extern bool xive_spapr_init(void);
extern bool xive_native_init(void);
extern void xive_smp_probe(void);
extern int xive_smp_prepare_cpu(unsigned int cpu);
extern void xive_smp_setup_cpu(void);
extern void xive_smp_disable_cpu(void);
+extern void xive_teardown_cpu(void);
extern void xive_kexec_teardown_cpu(int secondary);
