On Wed, 2008-03-19 at 17:10 +1100, Michael Ellerman wrote:
The PCI bridge representing the PCIE root complex on Axon, contains device
BARs for a memory range and ROM that define inbound accesses. This confuses
the kernel resource management code, the resources need to be hidden when
Axon is a
Michael Ellerman writes:
The PCI bridge representing the PCIE root complex on Axon, contains device
BARs for a memory range and ROM that define inbound accesses. This confuses
the kernel resource management code, the resources need to be hidden when
Axon is a host bridge.
Since you didn't
