Re: [PATCH] powerpc/32s: Slenderize _tlbia() for powerpc 603/603e

2020-03-05 Thread Michael Ellerman
On Mon, 2020-02-03 at 16:47:37 UTC, Christophe Leroy wrote:
> _tlbia() is a function used only on 603/603e core, ie on CPUs which
> don't have a hash table.
> 
> _tlbia() uses the tlbia macro which implements a loop of 1024 tlbie.
> 
> On the 603/603e core, flushing the entire TLB requires no more than
> 32 tlbie.
> 
> Replace tlbia by a loop of 32 tlbie.
> 
> Signed-off-by: Christophe Leroy 

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/e1347a020b81fe47c80cd277bfaa61295a9482a4

cheers


Re: [PATCH] powerpc/32s: Slenderize _tlbia() for powerpc 603/603e

2020-02-03 Thread Christophe Leroy




Le 03/02/2020 à 17:57, Joakim Tjernlund a écrit :

On Mon, 2020-02-03 at 16:47 +, Christophe Leroy wrote:

CAUTION: This email originated from outside of the organization. Do not click 
links or open attachments unless you recognize the sender and know the content 
is safe.


_tlbia() is a function used only on 603/603e core, ie on CPUs which
don't have a hash table.

_tlbia() uses the tlbia macro which implements a loop of 1024 tlbie.

On the 603/603e core, flushing the entire TLB requires no more than
32 tlbie.

Replace tlbia by a loop of 32 tlbie.

Signed-off-by: Christophe Leroy 
---
  arch/powerpc/mm/book3s32/hash_low.S | 13 -
  1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/mm/book3s32/hash_low.S 
b/arch/powerpc/mm/book3s32/hash_low.S
index c11b0a005196..a5039ad10429 100644
--- a/arch/powerpc/mm/book3s32/hash_low.S
+++ b/arch/powerpc/mm/book3s32/hash_low.S
@@ -696,18 +696,21 @@ _GLOBAL(_tlbia)
 bne-10b
 stwcx.  r8,0,r9
 bne-10b
+#endif /* CONFIG_SMP */
+   li  r5, 32
+   lis r4, KERNELBASE@h
+   mtctr   r5
 sync
-   tlbia
+0: tlbie   r4
+   addir4, r4, 0x1000


Is page size always 4096 here or does it not matter ?


603 and its derivatives (G2, e300, ...) only support 4k pages.

And regardless, the reference manual says:

The tlbia instruction is not implemented on the MPC603e and when its 
opcode is encountered, an illegal instruction program exception is 
generated. To invalidate all entries of both TLBs, 32 tlbie instructions 
must be executed, incrementing the value in EA[15–19] by 1 each time


Christophe


Re: [PATCH] powerpc/32s: Slenderize _tlbia() for powerpc 603/603e

2020-02-03 Thread Joakim Tjernlund
On Mon, 2020-02-03 at 16:47 +, Christophe Leroy wrote:
> CAUTION: This email originated from outside of the organization. Do not click 
> links or open attachments unless you recognize the sender and know the 
> content is safe.
> 
> 
> _tlbia() is a function used only on 603/603e core, ie on CPUs which
> don't have a hash table.
> 
> _tlbia() uses the tlbia macro which implements a loop of 1024 tlbie.
> 
> On the 603/603e core, flushing the entire TLB requires no more than
> 32 tlbie.
> 
> Replace tlbia by a loop of 32 tlbie.
> 
> Signed-off-by: Christophe Leroy 
> ---
>  arch/powerpc/mm/book3s32/hash_low.S | 13 -
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/powerpc/mm/book3s32/hash_low.S 
> b/arch/powerpc/mm/book3s32/hash_low.S
> index c11b0a005196..a5039ad10429 100644
> --- a/arch/powerpc/mm/book3s32/hash_low.S
> +++ b/arch/powerpc/mm/book3s32/hash_low.S
> @@ -696,18 +696,21 @@ _GLOBAL(_tlbia)
> bne-10b
> stwcx.  r8,0,r9
> bne-10b
> +#endif /* CONFIG_SMP */
> +   li  r5, 32
> +   lis r4, KERNELBASE@h
> +   mtctr   r5
> sync
> -   tlbia
> +0: tlbie   r4
> +   addir4, r4, 0x1000

Is page size always 4096 here or does it not matter ?

> +   bdnz0b
> sync
> +#ifdef CONFIG_SMP
> TLBSYNC
> li  r0,0
> stw r0,0(r9)/* clear mmu_hash_lock */
> mtmsr   r10
> SYNC_601
> isync
> -#else /* CONFIG_SMP */
> -   sync
> -   tlbia
> -   sync
>  #endif /* CONFIG_SMP */
> blr
> --
> 2.25.0
>