Re: [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers
On 03/08/2018 01:58 AM, Ram Pai wrote: On Wed, Mar 07, 2018 at 07:06:44PM +0530, Aneesh Kumar K.V wrote: Memory keys are supported only with hash translation mode. Instead of #ifdef in generic code move the key related pte bits to respective headers Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-4k.h | 7 +++ arch/powerpc/include/asm/book3s/64/hash-64k.h | 7 +++ arch/powerpc/include/asm/book3s/64/pgtable.h | 19 --- 3 files changed, 14 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h index fc3dc6a93939..4103bfc7c223 100644 --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h @@ -33,6 +33,13 @@ #define H_PAGE_THP_HUGE 0x0 #define H_PAGE_COMBO 0x0 +/* memory key bits, only 8 keys supported */ +#define H_PTE_PKEY_BIT00 +#define H_PTE_PKEY_BIT10 +#define H_PTE_PKEY_BIT2_RPAGE_RSV3 +#define H_PTE_PKEY_BIT3_RPAGE_RSV4 +#define H_PTE_PKEY_BIT4_RPAGE_RSV5 + If CONFIG_PPC_MEM_KEYS is not defined, all of them have to be 0. How is that handled here? why? conditional defines of pte bits always results in error, like we check for an overloaded key bit in some code path and taking wrong action. /* 8 bytes per each pte entry */ #define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3) #define H_PTE_FRAG_NR (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT) diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h index e53728ff29a0..bb880c97b87d 100644 --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h @@ -16,6 +16,13 @@ #define H_PAGE_BUSY _RPAGE_RPN44 /* software: PTE & hash are busy */ #define H_PAGE_HASHPTE_RPAGE_RPN43/* PTE has associated HPTE */ +/* memory key bits. */ +#define H_PTE_PKEY_BIT0_RPAGE_RSV1 +#define H_PTE_PKEY_BIT1_RPAGE_RSV2 +#define H_PTE_PKEY_BIT2_RPAGE_RSV3 +#define H_PTE_PKEY_BIT3_RPAGE_RSV4 +#define H_PTE_PKEY_BIT4_RPAGE_RSV5 + same comment as above. -aneesh
Re: [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers
On Wed, Mar 07, 2018 at 07:06:44PM +0530, Aneesh Kumar K.V wrote: > Memory keys are supported only with hash translation mode. Instead of #ifdef > in > generic code move the key related pte bits to respective headers > > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/book3s/64/hash-4k.h | 7 +++ > arch/powerpc/include/asm/book3s/64/hash-64k.h | 7 +++ > arch/powerpc/include/asm/book3s/64/pgtable.h | 19 --- > 3 files changed, 14 insertions(+), 19 deletions(-) > > diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h > b/arch/powerpc/include/asm/book3s/64/hash-4k.h > index fc3dc6a93939..4103bfc7c223 100644 > --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h > +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h > @@ -33,6 +33,13 @@ > #define H_PAGE_THP_HUGE 0x0 > #define H_PAGE_COMBO 0x0 > > +/* memory key bits, only 8 keys supported */ > +#define H_PTE_PKEY_BIT0 0 > +#define H_PTE_PKEY_BIT1 0 > +#define H_PTE_PKEY_BIT2 _RPAGE_RSV3 > +#define H_PTE_PKEY_BIT3 _RPAGE_RSV4 > +#define H_PTE_PKEY_BIT4 _RPAGE_RSV5 > + If CONFIG_PPC_MEM_KEYS is not defined, all of them have to be 0. How is that handled here? > /* 8 bytes per each pte entry */ > #define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3) > #define H_PTE_FRAG_NR(PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT) > diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h > b/arch/powerpc/include/asm/book3s/64/hash-64k.h > index e53728ff29a0..bb880c97b87d 100644 > --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h > +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h > @@ -16,6 +16,13 @@ > #define H_PAGE_BUSY _RPAGE_RPN44 /* software: PTE & hash are busy */ > #define H_PAGE_HASHPTE _RPAGE_RPN43/* PTE has associated HPTE */ > > +/* memory key bits. */ > +#define H_PTE_PKEY_BIT0 _RPAGE_RSV1 > +#define H_PTE_PKEY_BIT1 _RPAGE_RSV2 > +#define H_PTE_PKEY_BIT2 _RPAGE_RSV3 > +#define H_PTE_PKEY_BIT3 _RPAGE_RSV4 > +#define H_PTE_PKEY_BIT4 _RPAGE_RSV5 > + same comment as above. RP
