Re: [PATCH V3] cxl: Fixes for Coherent Accelerator Interface Architecture 2.0

2017-06-14 Thread Frederic Barrat 



Le 13/06/2017 à 17:41, Christophe Lombard a écrit :

A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards. These patches have been tested on Simulation environment and
quite a bit of them have been tested on real hardware.

This patch brings new fixes after a series of tests carried out on
new equipment:
* Add POWER9 definition.
* Re-enable any masked interrupts when the AFU is not activated after
   resetting the AFU.
* Remove the api cxl_is_psl8/9 which is no longer useful.
* Do not dump CAPI1 registers.
* Rewrite cxl_is_page_fault() function.
* Do not register slb callack on P9.

Changelog[v3]
  - Rebase to latest upstream.
  - Update the patch's header.
  - Add new test in cxl_is_page_fault().

Changelog[v2]
  - Rebase to latest upstream.
  - Update cxl_is_page_fault() to handle the checkout response status.
  - Add comments.

Signed-off-by: Christophe Lombard 
---


Looks good to me, thanks!
Acked-by: Frederic Barrat 




  drivers/misc/cxl/context.c |  6 +++---
  drivers/misc/cxl/cxl.h | 18 +-
  drivers/misc/cxl/fault.c   | 23 +++
  drivers/misc/cxl/main.c| 17 +
  drivers/misc/cxl/native.c  | 29 +
  drivers/misc/cxl/pci.c | 11 ---
  6 files changed, 57 insertions(+), 47 deletions(-)

diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c
index 4472ce1..8c32040 100644
--- a/drivers/misc/cxl/context.c
+++ b/drivers/misc/cxl/context.c
@@ -45,7 +45,7 @@ int cxl_context_init(struct cxl_context *ctx, struct cxl_afu 
*afu, bool master)
mutex_init(>mapping_lock);
ctx->mapping = NULL;

-   if (cxl_is_psl8(afu)) {
+   if (cxl_is_power8()) {
spin_lock_init(>sste_lock);

/*
@@ -189,7 +189,7 @@ int cxl_context_iomap(struct cxl_context *ctx, struct 
vm_area_struct *vma)
if (start + len > ctx->afu->adapter->ps_size)
return -EINVAL;

-   if (cxl_is_psl9(ctx->afu)) {
+   if (cxl_is_power9()) {
/*
 * Make sure there is a valid problem state
 * area space for this AFU.
@@ -324,7 +324,7 @@ static void reclaim_ctx(struct rcu_head *rcu)
  {
struct cxl_context *ctx = container_of(rcu, struct cxl_context, rcu);

-   if (cxl_is_psl8(ctx->afu))
+   if (cxl_is_power8())
free_page((u64)ctx->sstp);
if (ctx->ff_page)
__free_page(ctx->ff_page);
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index c8568ea..a03f8e7 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -357,6 +357,7 @@ static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
  #define CXL_PSL9_DSISR_An_PF_RGP  0x0090ULL  /* PTE not found 
(Radix Guest (parent)) 0b1001 */
  #define CXL_PSL9_DSISR_An_PF_HRH  0x0094ULL  /* PTE not found 
(HPT/Radix Host)   0b10010100 */
  #define CXL_PSL9_DSISR_An_PF_STEG 0x009CULL  /* PTE not found 
(STEG VA)  0b10011100 */
+#define CXL_PSL9_DSISR_An_URTCH   0x00B4ULL  /* Unsupported Radix 
Tree Configuration 0b10110100 */

  /** CXL_PSL_TFC_An **/
  #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation 
fault */
@@ -844,24 +845,15 @@ static inline bool cxl_is_power8(void)

  static inline bool cxl_is_power9(void)
  {
-   /* intermediate solution */
-   if (!cxl_is_power8() &&
-  (cpu_has_feature(CPU_FTRS_POWER9) ||
-   cpu_has_feature(CPU_FTR_POWER9_DD1)))
+   if (pvr_version_is(PVR_POWER9))
return true;
return false;
  }

-static inline bool cxl_is_psl8(struct cxl_afu *afu)
+static inline bool cxl_is_power9_dd1(void)
  {
-   if (afu->adapter->caia_major == 1)
-   return true;
-   return false;
-}
-
-static inline bool cxl_is_psl9(struct cxl_afu *afu)
-{
-   if (afu->adapter->caia_major == 2)
+   if ((pvr_version_is(PVR_POWER9)) &&
+   cpu_has_feature(CPU_FTR_POWER9_DD1))
return true;
return false;
  }
diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c
index 538..c79e39b 100644
--- a/drivers/misc/cxl/fault.c
+++ b/drivers/misc/cxl/fault.c
@@ -187,7 +187,7 @@ static struct mm_struct *get_mem_context(struct cxl_context 
*ctx)

  static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)
  {
-   if ((cxl_is_psl8(ctx->afu)) && (dsisr & CXL_PSL_DSISR_An_DS))
+   if ((cxl_is_power8() && (dsisr & CXL_PSL_DSISR_An_DS)))
return true;

return false;
@@ -195,16 +195,23 @@ static bool cxl_is_segment_miss(struct cxl_context *ctx, 
u64 dsisr)

  static bool cxl_is_page_fault(struct cxl_context *ctx, u64

Re: [PATCH V3] cxl: Fixes for Coherent Accelerator Interface Architecture 2.0

2017-06-14 Thread christophe lombard 

Le 14/06/2017 à 07:01, Michael Ellerman a écrit :

Christophe Lombard  writes:


A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards.

Which commit is that?

cheers


Here are the commit ids of the patchset:
cxl: Add support for Coherent Accelerator Interface Architecture 2.0

patch1: aba81433b50350fde68bf80fe9f75d671e15b5ae
patch2: 66ef20c7834b7df18168b12a57ef01c6ae0d1a81
patch3: 6dd2d23403396d8e6d153a6c9db56e1a1012bad8
patch4: bdd2e7150644fee4de7167a3e08294ef32eeda11
patch5: 64663f372c72cedeba1b1dc86df9cc159ae5a93d
patch6: abd1d99bb3da42d6c7341c14986f5b8f4dcc6bd5
patch7: f24be42aab37c6d07c05126673138e06223a6399

Thanks


These patches have been tested on Simulation environment and
quite a bit of them have been tested on real hardware.

This patch brings new fixes after a series of tests carried out on
new equipment:
* Add POWER9 definition.
* Re-enable any masked interrupts when the AFU is not activated after
   resetting the AFU.
* Remove the api cxl_is_psl8/9 which is no longer useful.
* Do not dump CAPI1 registers.
* Rewrite cxl_is_page_fault() function.
* Do not register slb callack on P9.

Changelog[v3]
  - Rebase to latest upstream.
  - Update the patch's header.
  - Add new test in cxl_is_page_fault().

Changelog[v2]
  - Rebase to latest upstream.
  - Update cxl_is_page_fault() to handle the checkout response status.
  - Add comments.

Signed-off-by: Christophe Lombard 
---
  drivers/misc/cxl/context.c |  6 +++---
  drivers/misc/cxl/cxl.h | 18 +-
  drivers/misc/cxl/fault.c   | 23 +++
  drivers/misc/cxl/main.c| 17 +
  drivers/misc/cxl/native.c  | 29 +
  drivers/misc/cxl/pci.c | 11 ---
  6 files changed, 57 insertions(+), 47 deletions(-)

diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c
index 4472ce1..8c32040 100644
--- a/drivers/misc/cxl/context.c
+++ b/drivers/misc/cxl/context.c
@@ -45,7 +45,7 @@ int cxl_context_init(struct cxl_context *ctx, struct cxl_afu 
*afu, bool master)
mutex_init(>mapping_lock);
ctx->mapping = NULL;
  
-	if (cxl_is_psl8(afu)) {

+   if (cxl_is_power8()) {
spin_lock_init(>sste_lock);
  
  		/*

@@ -189,7 +189,7 @@ int cxl_context_iomap(struct cxl_context *ctx, struct 
vm_area_struct *vma)
if (start + len > ctx->afu->adapter->ps_size)
return -EINVAL;
  
-		if (cxl_is_psl9(ctx->afu)) {

+   if (cxl_is_power9()) {
/*
 * Make sure there is a valid problem state
 * area space for this AFU.
@@ -324,7 +324,7 @@ static void reclaim_ctx(struct rcu_head *rcu)
  {
struct cxl_context *ctx = container_of(rcu, struct cxl_context, rcu);
  
-	if (cxl_is_psl8(ctx->afu))

+   if (cxl_is_power8())
free_page((u64)ctx->sstp);
if (ctx->ff_page)
__free_page(ctx->ff_page);
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index c8568ea..a03f8e7 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -357,6 +357,7 @@ static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
  #define CXL_PSL9_DSISR_An_PF_RGP  0x0090ULL  /* PTE not found 
(Radix Guest (parent)) 0b1001 */
  #define CXL_PSL9_DSISR_An_PF_HRH  0x0094ULL  /* PTE not found 
(HPT/Radix Host)   0b10010100 */
  #define CXL_PSL9_DSISR_An_PF_STEG 0x009CULL  /* PTE not found 
(STEG VA)  0b10011100 */
+#define CXL_PSL9_DSISR_An_URTCH   0x00B4ULL  /* Unsupported Radix 
Tree Configuration 0b10110100 */
  
  /** CXL_PSL_TFC_An **/

  #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation 
fault */
@@ -844,24 +845,15 @@ static inline bool cxl_is_power8(void)
  
  static inline bool cxl_is_power9(void)

  {
-   /* intermediate solution */
-   if (!cxl_is_power8() &&
-  (cpu_has_feature(CPU_FTRS_POWER9) ||
-   cpu_has_feature(CPU_FTR_POWER9_DD1)))
+   if (pvr_version_is(PVR_POWER9))
return true;
return false;
  }
  
-static inline bool cxl_is_psl8(struct cxl_afu *afu)

+static inline bool cxl_is_power9_dd1(void)
  {
-   if (afu->adapter->caia_major == 1)
-   return true;
-   return false;
-}
-
-static inline bool cxl_is_psl9(struct cxl_afu *afu)
-{
-   if (afu->adapter->caia_major == 2)
+   if ((pvr_version_is(PVR_POWER9)) &&
+   cpu_has_feature(CPU_FTR_POWER9_DD1))
return true;
return false;
  }
diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c
index 538..c79e39b 100644
--- a/drivers/misc/cxl/fault.c
+++ b/drivers/misc/cxl/fault.c
@@ -187,7 +187,7 @@ static struct mm_struct

Re: [PATCH V3] cxl: Fixes for Coherent Accelerator Interface Architecture 2.0

2017-06-13 Thread Michael Ellerman 
Christophe Lombard  writes:

> A previous set of patches "cxl: Add support for Coherent Accelerator
> Interface Architecture 2.0" has introduced a new support for the CAPI
> cards.

Which commit is that?

cheers

> These patches have been tested on Simulation environment and
> quite a bit of them have been tested on real hardware.
>
> This patch brings new fixes after a series of tests carried out on
> new equipment:
> * Add POWER9 definition.
> * Re-enable any masked interrupts when the AFU is not activated after
>   resetting the AFU.
> * Remove the api cxl_is_psl8/9 which is no longer useful.
> * Do not dump CAPI1 registers.
> * Rewrite cxl_is_page_fault() function.
> * Do not register slb callack on P9.
>
> Changelog[v3]
>  - Rebase to latest upstream.
>  - Update the patch's header.
>  - Add new test in cxl_is_page_fault().
>
> Changelog[v2]
>  - Rebase to latest upstream.
>  - Update cxl_is_page_fault() to handle the checkout response status.
>  - Add comments.
>
> Signed-off-by: Christophe Lombard 
> ---
>  drivers/misc/cxl/context.c |  6 +++---
>  drivers/misc/cxl/cxl.h | 18 +-
>  drivers/misc/cxl/fault.c   | 23 +++
>  drivers/misc/cxl/main.c| 17 +
>  drivers/misc/cxl/native.c  | 29 +
>  drivers/misc/cxl/pci.c | 11 ---
>  6 files changed, 57 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c
> index 4472ce1..8c32040 100644
> --- a/drivers/misc/cxl/context.c
> +++ b/drivers/misc/cxl/context.c
> @@ -45,7 +45,7 @@ int cxl_context_init(struct cxl_context *ctx, struct 
> cxl_afu *afu, bool master)
>   mutex_init(>mapping_lock);
>   ctx->mapping = NULL;
>  
> - if (cxl_is_psl8(afu)) {
> + if (cxl_is_power8()) {
>   spin_lock_init(>sste_lock);
>  
>   /*
> @@ -189,7 +189,7 @@ int cxl_context_iomap(struct cxl_context *ctx, struct 
> vm_area_struct *vma)
>   if (start + len > ctx->afu->adapter->ps_size)
>   return -EINVAL;
>  
> - if (cxl_is_psl9(ctx->afu)) {
> + if (cxl_is_power9()) {
>   /*
>* Make sure there is a valid problem state
>* area space for this AFU.
> @@ -324,7 +324,7 @@ static void reclaim_ctx(struct rcu_head *rcu)
>  {
>   struct cxl_context *ctx = container_of(rcu, struct cxl_context, rcu);
>  
> - if (cxl_is_psl8(ctx->afu))
> + if (cxl_is_power8())
>   free_page((u64)ctx->sstp);
>   if (ctx->ff_page)
>   __free_page(ctx->ff_page);
> diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
> index c8568ea..a03f8e7 100644
> --- a/drivers/misc/cxl/cxl.h
> +++ b/drivers/misc/cxl/cxl.h
> @@ -357,6 +357,7 @@ static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
>  #define CXL_PSL9_DSISR_An_PF_RGP  0x0090ULL  /* PTE not found 
> (Radix Guest (parent)) 0b1001 */
>  #define CXL_PSL9_DSISR_An_PF_HRH  0x0094ULL  /* PTE not found 
> (HPT/Radix Host)   0b10010100 */
>  #define CXL_PSL9_DSISR_An_PF_STEG 0x009CULL  /* PTE not found 
> (STEG VA)  0b10011100 */
> +#define CXL_PSL9_DSISR_An_URTCH   0x00B4ULL  /* Unsupported 
> Radix Tree Configuration 0b10110100 */
>  
>  /** CXL_PSL_TFC_An 
> **/
>  #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation 
> fault */
> @@ -844,24 +845,15 @@ static inline bool cxl_is_power8(void)
>  
>  static inline bool cxl_is_power9(void)
>  {
> - /* intermediate solution */
> - if (!cxl_is_power8() &&
> -(cpu_has_feature(CPU_FTRS_POWER9) ||
> - cpu_has_feature(CPU_FTR_POWER9_DD1)))
> + if (pvr_version_is(PVR_POWER9))
>   return true;
>   return false;
>  }
>  
> -static inline bool cxl_is_psl8(struct cxl_afu *afu)
> +static inline bool cxl_is_power9_dd1(void)
>  {
> - if (afu->adapter->caia_major == 1)
> - return true;
> - return false;
> -}
> -
> -static inline bool cxl_is_psl9(struct cxl_afu *afu)
> -{
> - if (afu->adapter->caia_major == 2)
> + if ((pvr_version_is(PVR_POWER9)) &&
> + cpu_has_feature(CPU_FTR_POWER9_DD1))
>   return true;
>   return false;
>  }
> diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c
> index 538..c79e39b 100644
> --- a/drivers/misc/cxl/fault.c
> +++ b/drivers/misc/cxl/fault.c
> @@ -187,7 +187,7 @@ static struct mm_struct *get_mem_context(struct 
> cxl_context *ctx)
>  
>  static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)
>  {
> - if ((cxl_is_psl8(ctx->afu)) && (dsisr & CXL_PSL_DSISR_An_DS))
> + if ((cxl_is_power8() && (dsisr & CXL_PSL_DSISR_An_DS)))
>   return true;
>  
>   return false;
> @@ -195,16 +195,23 @@ static bool