On Tue, 2014-01-07 at 15:22 +0800, wyang wrote:
On 01/07/2014 02:35 PM, Scott Wood wrote:
On Tue, 2014-01-07 at 09:00 +0800, wyang wrote:
Yeah, Can you provide more detail info about why they can handle that
case? The following is my understand:
Let us assume that there is a atomic
On Mon, 2014-01-06 at 13:27 +0800, wyang wrote:
On 01/06/2014 11:41 AM, Gavin Hu wrote:
Thanks your response. :)
But that means that these optimitive operations like atomic_add()
aren't optimitive actully in PPC architecture, right? Becuase they
can be interrupted by loacl HW
On 01/07/2014 06:05 AM, Scott Wood wrote:
On Mon, 2014-01-06 at 13:27 +0800, wyang wrote:
On 01/06/2014 11:41 AM, Gavin Hu wrote:
Thanks your response. :)
But that means that these optimitive operations like atomic_add()
aren't optimitive actully in PPC architecture, right? Becuase they
can
On Tue, 2014-01-07 at 09:00 +0800, wyang wrote:
Yeah, Can you provide more detail info about why they can handle that
case? The following is my understand:
Let us assume that there is a atomic global variable(var_a) and its
initial value is 0.
The kernel attempts to execute
On 01/07/2014 02:35 PM, Scott Wood wrote:
On Tue, 2014-01-07 at 09:00 +0800, wyang wrote:
Yeah, Can you provide more detail info about why they can handle that
case? The following is my understand:
Let us assume that there is a atomic global variable(var_a) and its
initial value is 0.
The
Thanks your response. :)
But that means that these optimitive operations like atomic_add() aren't
optimitive actully in PPC architecture, right? Becuase they can be
interrupted by loacl HW interrupts. Theoretically, the ISR also can access
the atomic gloable variable.
The following codes are
Get it. Thanks! :)
BR
Gavin. Hu
On Mon, Jan 6, 2014 at 1:27 PM, wyang w90p...@gmail.com wrote:
On 01/06/2014 11:41 AM, Gavin Hu wrote:
Thanks your response. :)
But that means that these optimitive operations like atomic_add() aren't
optimitive actully in PPC architecture, right?
So, these primitive funcitons like atomic_add() and so on also can't
prevent processes schedule switch on local CPU core? right?
Thanks!
BR
Gvain. Hu
On Mon, Jan 6, 2014 at 1:27 PM, wyang w90p...@gmail.com wrote:
On 01/06/2014 11:41 AM, Gavin Hu wrote:
Thanks your response. :)
But
On 01/06/2014 02:24 PM, Gavin Hu wrote:
So, these primitive funcitons like atomic_add() and so on also can't
prevent processes schedule switch on local CPU core? right?
You are right!
BR
Wei
Thanks!
BR
Gvain. Hu
On Mon, Jan 6, 2014 at 1:27 PM, wyang w90p...@gmail.com
On 12/28/2013 01:41 PM, Gavin Hu wrote:
Hi
I notice that there is a pair ppc instructions lwarx and stwcx used to
atomtic operation for instance, atomic_inc/atomic_dec.
In some ppc manuals, they more emphasize its mechanism is that lwarx
can reseve the target memory address preventing other
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