On Fri, Mar 14, 2014 at 05:35:09PM +0000, Vick, Matthew wrote: > Reading a PCIe register is tricky, since it has to flush any posted > transactions (meaning all PCIe writes have to complete), send the read > request, and then actually get the result. It's also important to note > that reading the clock on i210 is 3 PCIe reads.
This is very interesting information. I'm wondering if it would make sense to describe this in the ptp_clock_caps struct as a ratio between the request and reply delay to allow more accurate transfer of time from the PHC to the system clock. Currently, the offset is calculated as (TS1 + TS2) / 2 - TP, where TS1 and TS2 are system clock readings made right before and after PHC reading (TP). In this case something like (TS1 + TS2 * 5) / 6 - TP would possibly be more accurate. -- Miroslav Lichvar ------------------------------------------------------------------------------ Learn Graph Databases - Download FREE O'Reilly Book "Graph Databases" is the definitive new guide to graph databases and their applications. Written by three acclaimed leaders in the field, this first edition is now available. Download your free book today! http://p.sf.net/sfu/13534_NeoTech _______________________________________________ Linuxptp-devel mailing list Linuxptp-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/linuxptp-devel
