[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

omjavaid added a comment. In D77045#1963896 , @labath wrote: > In D77045#1956879 , @omjavaid wrote: > > > Adding a testcase would be tricky as these register overlap in memory and > > we store them with

[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

labath added a comment. In D77045#1956879 , @omjavaid wrote: > Adding a testcase would be tricky as these register overlap in memory and we > store them with overlapping offsets with their children we should not need to > invalidate the children when we

[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

omjavaid marked an inline comment as done. omjavaid added a comment. In D77045#1954690 , @labath wrote: > This sounds like it could use a test case. Adding a testcase would be tricky as these register overlap in memory and we store them with

[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

labath added a comment. This sounds like it could use a test case. Comment at: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h:593-594 +#define STRINGIZE2(x) #x +#define STRINGIZE(x) STRINGIZE2(x) + What's up with the indirection? CHANGES SINCE

[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

omjavaid created this revision. omjavaid added a reviewer: labath. Herald added subscribers: danielkiss, kristof.beyls. AArch64 reigster X and V registers are primary GPR and vector registers respectively. If these registers are modified their corresponding children w regs or s/d regs should be