[Lldb-commits] [PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.
sdesmalen marked 2 inline comments as done.
sdesmalen added inline comments.
Comment at: clang/include/clang/Basic/AArch64SVEACLETypes.def:69
-SVE_VECTOR_TYPE("__SVBFloat16_t", "__SVBFloat16_t", SveBFloat16,
SveBFloat16Ty, 8, 16, false, false, true)
+SVE_VECTOR_TYPE("__SVBFloat16_t", "__SVBFloat16_t", SveBFloat16,
SveBFloat16Ty, 8, 16, true, false, true)
fpetrogalli wrote:
> Why did you have to set `IsFP = true`? Seems like an unrelated change?
It's more for consistency with the other definitions (svfloat16/svfloat32/..)
but is otherwise a non-functional change.
Comment at: clang/utils/TableGen/SveEmitter.cpp:541
Float = false;
+BFloat = false;
ElementBitwidth /= 4;
fpetrogalli wrote:
> Are these needed? I don't understand the rule for when to be specific on the
> values of these variables.
For this patch, it's needed for `'l'` because otherwise it will incorrectly
assume the type is bfloat if the type specifier is `b`.
It similarly applies to all the other modifiers that are defined as being of
type `integer`.
Repository:
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[Lldb-commits] [PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.
sdesmalen updated this revision to Diff 272342.
sdesmalen added a comment.
- Updated RUN line in tests to fix test failures.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82187/new/
https://reviews.llvm.org/D82187
Files:
clang/include/clang/Basic/AArch64SVEACLETypes.def
clang/include/clang/Basic/arm_sve.td
clang/lib/CodeGen/CodeGenTypes.cpp
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
clang/utils/TableGen/SveEmitter.cpp
lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
; WARN-NOT: warning
@@ -44,6 +44,17 @@
ret void
}
+define void @st2h_bf16( %v0, %v1, %pred, bfloat* %addr) {
+; CHECK-LABEL: st2h_bf16:
+; CHECK: st2h { z0.h, z1.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st2.nxv8bf16( %v0,
+ %v1,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST2W
;
@@ -140,6 +151,18 @@
ret void
}
+define void @st3h_bf16( %v0, %v1, %v2, %pred, bfloat* %addr) {
+; CHECK-LABEL: st3h_bf16:
+; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st3.nxv8bf16( %v0,
+ %v1,
+ %v2,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST3W
;
@@ -243,6 +266,19 @@
ret void
}
+define void @st4h_bf16( %v0, %v1, %v2, %v3, %pred, bfloat* %addr) {
+; CHECK-LABEL: st4h_bf16:
+; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st4.nxv8bf16( %v0,
+ %v1,
+ %v2,
+ %v3,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST4W
;
@@ -395,6 +431,7 @@
declare void @llvm.aarch64.sve.st2.nxv4i32(, , , i32*)
declare void @llvm.aarch64.sve.st2.nxv2i64(, , , i64*)
declare void @llvm.aarch64.sve.st2.nxv8f16(, , , half*)
+declare void @llvm.aarch64.sve.st2.nxv8bf16(, , , bfloat*)
declare void @llvm.aarch64.sve.st2.nxv4f32(, , , float*)
declare void @llvm.aarch64.sve.st2.nxv2f64(, , , double*)
@@ -403,6 +440,7 @@
declare void @llvm.aarch64.sve.st3.nxv4i32(, , , , i32*)
declare void @llvm.aarch64.sve.st3.nxv2i64(, , , , i64*)
declare void @llvm.aarch64.sve.st3.nxv8f16(, , , , half*)
+declare void @llvm.aarch64.sve.st3.nxv8bf16(, , , , bfloat*)
declare void @llvm.aarch64.sve.st3.nxv4f32(, , , , float*)
declare void @llvm.aarch64.sve.st3.nxv2f64(, , , , double*)
@@ -411,6 +449,7 @@
declare void @llvm.aarch64.sve.st4.nxv4i32(, , , , , i32*)
declare void @llvm.aarch64.sve.st4.nxv2i64(, , , , , i64*)
declare void @llvm.aarch64.sve.st4.nxv8f16(, , , , , half*)
+declare void @llvm.aarch64.sve.st4.nxv8bf16(, , , , , bfloat*)
declare void @llvm.aarch64.sve.st4.nxv4f32(, , , , , float*)
declare void @llvm.aarch64.sve.st4.nxv2f64(, , , , , double*)
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 -asm-verbose=0 < %s | FileCheck %s
;
; LD1RQB
@@ -284,6 +284,14 @@
ret %res
}
+define @ld2h_bf16( %pred, bfloat* %addr) {
+; CHECK-LABEL: ld2h_bf16:
+; CHECK: ld2h { z0.h, z1.h }, p0/z, [x0]
+; CHECK-NEXT: ret
+ %res = call @llvm.aarch64.sve.ld2.nxv16bf16.nxv8i1.p0bf16( %pred, bfloat* %addr)
+ ret %res
+}
+
;
; LD2W
;
@@ -356,6 +364,14 @@
ret %res
}
+define @ld3h_bf16( %pred, bfloat* %addr) {
+; CHECK-LABEL: ld3h_bf16:
+; CHECK: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0]
+;
[Lldb-commits] [PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.
fpetrogalli added inline comments.
Comment at: clang/include/clang/Basic/AArch64SVEACLETypes.def:69
-SVE_VECTOR_TYPE("__SVBFloat16_t", "__SVBFloat16_t", SveBFloat16,
SveBFloat16Ty, 8, 16, false, false, true)
+SVE_VECTOR_TYPE("__SVBFloat16_t", "__SVBFloat16_t", SveBFloat16,
SveBFloat16Ty, 8, 16, true, false, true)
Why did you have to set `IsFP = true`? Seems like an unrelated change?
Comment at: clang/utils/TableGen/SveEmitter.cpp:541
Float = false;
+BFloat = false;
ElementBitwidth /= 4;
Are these needed? I don't understand the rule for when to be specific on the
values of these variables.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82187/new/
https://reviews.llvm.org/D82187
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[Lldb-commits] [PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.
sdesmalen created this revision.
sdesmalen added reviewers: stuij, efriedma, c-rhodes, fpetrogalli.
Herald added subscribers: llvm-commits, lldb-commits, cfe-commits, danielkiss,
psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added projects: clang, LLDB, LLVM.
sdesmalen added a parent revision: D82178: [AArch64][SVE] Guard svbfloat16_t
with feature macro in ACLE.
This patch contains:
- Support in LLVM CodeGen for bfloat16 types for ld2/3/4 and st2/3/4.
- New bfloat16 ACLE builtins for svld(2|3|4)[_vnum] and svst(2|3|4)[_vnum]
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D82187
Files:
clang/include/clang/Basic/AArch64SVEACLETypes.def
clang/include/clang/Basic/arm_sve.td
clang/lib/CodeGen/CodeGenTypes.cpp
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
clang/utils/TableGen/SveEmitter.cpp
lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
; WARN-NOT: warning
@@ -44,6 +44,17 @@
ret void
}
+define void @st2h_bf16( %v0, %v1, %pred, bfloat* %addr) {
+; CHECK-LABEL: st2h_bf16:
+; CHECK: st2h { z0.h, z1.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st2.nxv8bf16( %v0,
+ %v1,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST2W
;
@@ -140,6 +151,18 @@
ret void
}
+define void @st3h_bf16( %v0, %v1, %v2, %pred, bfloat* %addr) {
+; CHECK-LABEL: st3h_bf16:
+; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st3.nxv8bf16( %v0,
+ %v1,
+ %v2,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST3W
;
@@ -243,6 +266,19 @@
ret void
}
+define void @st4h_bf16( %v0, %v1, %v2, %v3, %pred, bfloat* %addr) {
+; CHECK-LABEL: st4h_bf16:
+; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st4.nxv8bf16( %v0,
+ %v1,
+ %v2,
+ %v3,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST4W
;
@@ -395,6 +431,7 @@
declare void @llvm.aarch64.sve.st2.nxv4i32(, , , i32*)
declare void @llvm.aarch64.sve.st2.nxv2i64(, , , i64*)
declare void @llvm.aarch64.sve.st2.nxv8f16(, , , half*)
+declare void @llvm.aarch64.sve.st2.nxv8bf16(, , , bfloat*)
declare void @llvm.aarch64.sve.st2.nxv4f32(, , , float*)
declare void @llvm.aarch64.sve.st2.nxv2f64(, , , double*)
@@ -403,6 +440,7 @@
declare void @llvm.aarch64.sve.st3.nxv4i32(, , , , i32*)
declare void @llvm.aarch64.sve.st3.nxv2i64(, , , , i64*)
declare void @llvm.aarch64.sve.st3.nxv8f16(, , , , half*)
+declare void @llvm.aarch64.sve.st3.nxv8bf16(, , , , bfloat*)
declare void @llvm.aarch64.sve.st3.nxv4f32(, , , , float*)
declare void @llvm.aarch64.sve.st3.nxv2f64(, , , , double*)
@@ -411,6 +449,7 @@
declare void @llvm.aarch64.sve.st4.nxv4i32(, , , , , i32*)
declare void @llvm.aarch64.sve.st4.nxv2i64(, , , , , i64*)
declare void @llvm.aarch64.sve.st4.nxv8f16(, , , , , half*)
+declare void @llvm.aarch64.sve.st4.nxv8bf16(, , , , , bfloat*)
declare void @llvm.aarch64.sve.st4.nxv4f32(, , , , , float*)
declare void @llvm.aarch64.sve.st4.nxv2f64(, , , , , double*)
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 -asm-verbose=0 < %s | FileCheck %s
;
; LD1RQB
@@ -284,6 +284,14 @@
ret %res
}
+define @ld2h_bf16(
[Lldb-commits] [PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG121e585ec8aa: [AArch64][SVE] ACLE: Add bfloat16 to struct
load/stores. (authored by sdesmalen).
Changed prior to commit:
https://reviews.llvm.org/D82187?vs=272342=272678#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82187/new/
https://reviews.llvm.org/D82187
Files:
clang/include/clang/Basic/AArch64SVEACLETypes.def
clang/include/clang/Basic/arm_sve.td
clang/lib/CodeGen/CodeGenTypes.cpp
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
clang/utils/TableGen/SveEmitter.cpp
lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
; WARN-NOT: warning
@@ -44,6 +44,17 @@
ret void
}
+define void @st2h_bf16( %v0, %v1, %pred, bfloat* %addr) {
+; CHECK-LABEL: st2h_bf16:
+; CHECK: st2h { z0.h, z1.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st2.nxv8bf16( %v0,
+ %v1,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST2W
;
@@ -140,6 +151,18 @@
ret void
}
+define void @st3h_bf16( %v0, %v1, %v2, %pred, bfloat* %addr) {
+; CHECK-LABEL: st3h_bf16:
+; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st3.nxv8bf16( %v0,
+ %v1,
+ %v2,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST3W
;
@@ -243,6 +266,19 @@
ret void
}
+define void @st4h_bf16( %v0, %v1, %v2, %v3, %pred, bfloat* %addr) {
+; CHECK-LABEL: st4h_bf16:
+; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sve.st4.nxv8bf16( %v0,
+ %v1,
+ %v2,
+ %v3,
+ %pred,
+ bfloat* %addr)
+ ret void
+}
+
;
; ST4W
;
@@ -395,6 +431,7 @@
declare void @llvm.aarch64.sve.st2.nxv4i32(, , , i32*)
declare void @llvm.aarch64.sve.st2.nxv2i64(, , , i64*)
declare void @llvm.aarch64.sve.st2.nxv8f16(, , , half*)
+declare void @llvm.aarch64.sve.st2.nxv8bf16(, , , bfloat*)
declare void @llvm.aarch64.sve.st2.nxv4f32(, , , float*)
declare void @llvm.aarch64.sve.st2.nxv2f64(, , , double*)
@@ -403,6 +440,7 @@
declare void @llvm.aarch64.sve.st3.nxv4i32(, , , , i32*)
declare void @llvm.aarch64.sve.st3.nxv2i64(, , , , i64*)
declare void @llvm.aarch64.sve.st3.nxv8f16(, , , , half*)
+declare void @llvm.aarch64.sve.st3.nxv8bf16(, , , , bfloat*)
declare void @llvm.aarch64.sve.st3.nxv4f32(, , , , float*)
declare void @llvm.aarch64.sve.st3.nxv2f64(, , , , double*)
@@ -411,6 +449,7 @@
declare void @llvm.aarch64.sve.st4.nxv4i32(, , , , , i32*)
declare void @llvm.aarch64.sve.st4.nxv2i64(, , , , , i64*)
declare void @llvm.aarch64.sve.st4.nxv8f16(, , , , , half*)
+declare void @llvm.aarch64.sve.st4.nxv8bf16(, , , , , bfloat*)
declare void @llvm.aarch64.sve.st4.nxv4f32(, , , , , float*)
declare void @llvm.aarch64.sve.st4.nxv2f64(, , , , , double*)
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 -asm-verbose=0 < %s | FileCheck %s
;
; LD1RQB
@@ -284,6 +284,14 @@
ret %res
}
+define @ld2h_bf16( %pred, bfloat* %addr) {
+; CHECK-LABEL: ld2h_bf16:
+; CHECK: ld2h { z0.h, z1.h }, p0/z, [x0]
+; CHECK-NEXT: ret
+ %res = call @llvm.aarch64.sve.ld2.nxv16bf16.nxv8i1.p0bf16( %pred, bfloat* %addr)
+ ret %res
+}
+
;
