[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/JDevlieghere closed https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
JDevlieghere wrote: The issue is closed. Your account and its associated PRs disappeared and since I was already familiar with the change , I landed it in https://github.com/llvm/llvm-project/pull/176472. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
MkDev11 wrote: Please review the changes when you are available, thanks. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 reopened https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 9bcd3415b706dac890e67ce2ffe0f98405f91fbf Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Thu, 15 Jan 2026 02:38:41 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 23 +++
.../Instruction/RISCV/TestRISCVEmulator.cpp | 17 ++
2 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..4f4e6779072d2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,8 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoInterface.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,10 +1839,23 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ std::unique_ptr reg_info;
+ switch (m_arch.GetTriple().getArch()) {
+ case llvm::Triple::riscv32:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+break;
+ case llvm::Triple::riscv64:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
+break;
+ default:
+assert(false && "unsupported triple");
+return {};
+ }
+
+ const RegisterInfo *array = reg_info->GetRegisterInfo();
+ const uint32_t length = reg_info->GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..f713755c77a7c 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,19 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for riscv64.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for riscv32.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 edited https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 9bcd3415b706dac890e67ce2ffe0f98405f91fbf Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Thu, 15 Jan 2026 02:38:41 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 23 +++
.../Instruction/RISCV/TestRISCVEmulator.cpp | 17 ++
2 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..4f4e6779072d2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,8 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoInterface.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,10 +1839,23 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ std::unique_ptr reg_info;
+ switch (m_arch.GetTriple().getArch()) {
+ case llvm::Triple::riscv32:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+break;
+ case llvm::Triple::riscv64:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
+break;
+ default:
+assert(false && "unsupported triple");
+return {};
+ }
+
+ const RegisterInfo *array = reg_info->GetRegisterInfo();
+ const uint32_t length = reg_info->GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..f713755c77a7c 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,19 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for riscv64.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for riscv32.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
JDevlieghere wrote: Repeated pings and emails attempting to rush reviewers are not acceptable. Both @DavidSpickett and I have now repeatedly tried to make this clear, but the behavior has continued. You just sent me another email and I'm seeing similar concerning behavior in https://github.com/llvm/llvm-project/pull/176076. It’s disruptive to both myself and other contributors who are volunteering their time to review. Reviews happen on a best-effort basis. Reviewers balance this work alongside many other responsibilities, and timelines are driven by availability. Please stop this behavior. I value your contributions and want them to succeed, but that requires respecting the project's culture and the time of the people involved. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 9bcd3415b706dac890e67ce2ffe0f98405f91fbf Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Thu, 15 Jan 2026 02:38:41 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 23 +++
.../Instruction/RISCV/TestRISCVEmulator.cpp | 17 ++
2 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..4f4e6779072d2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,8 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoInterface.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,10 +1839,23 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ std::unique_ptr reg_info;
+ switch (m_arch.GetTriple().getArch()) {
+ case llvm::Triple::riscv32:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+break;
+ case llvm::Triple::riscv64:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
+break;
+ default:
+assert(false && "unsupported triple");
+return {};
+ }
+
+ const RegisterInfo *array = reg_info->GetRegisterInfo();
+ const uint32_t length = reg_info->GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..f713755c77a7c 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,19 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for riscv64.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for riscv32.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
MkDev11 wrote: @JDevlieghere Can you merge the PR? https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
@@ -1837,10 +1839,22 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ std::unique_ptr reg_info;
+ switch (m_arch.GetTriple().getArch()) {
+ case llvm::Triple::riscv32:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+break;
+ case llvm::Triple::riscv64:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
+break;
+ default:
+return {};
MkDev11 wrote:
Done!
https://github.com/llvm/llvm-project/pull/175262
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 9bcd3415b706dac890e67ce2ffe0f98405f91fbf Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Thu, 15 Jan 2026 02:38:41 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 23 +++
.../Instruction/RISCV/TestRISCVEmulator.cpp | 17 ++
2 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..4f4e6779072d2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,8 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoInterface.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,10 +1839,23 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ std::unique_ptr reg_info;
+ switch (m_arch.GetTriple().getArch()) {
+ case llvm::Triple::riscv32:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+break;
+ case llvm::Triple::riscv64:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
+break;
+ default:
+assert(false && "unsupported triple");
+return {};
+ }
+
+ const RegisterInfo *array = reg_info->GetRegisterInfo();
+ const uint32_t length = reg_info->GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..f713755c77a7c 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,19 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for riscv64.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for riscv32.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
@@ -1837,10 +1839,22 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ std::unique_ptr reg_info;
+ switch (m_arch.GetTriple().getArch()) {
+ case llvm::Triple::riscv32:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+break;
+ case llvm::Triple::riscv64:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
+break;
+ default:
+return {};
JDevlieghere wrote:
I'm fine with returning here, but let's add an assert so this doesn't happen
silently.
```suggestion
assert(false && "unsupported triple");
return {};
```
https://github.com/llvm/llvm-project/pull/175262
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/JDevlieghere approved this pull request. LGTM with the assert added. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/JDevlieghere edited https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
JDevlieghere wrote: Looking at https://github.com/llvm/llvm-project/issues/175092, the attached patch is even simpler. Did that not work? If it does, we should go with that together with the new unit tests. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
MkDev11 wrote: Thanks for your feedback. I've updated the PR to use the simpler approach from the attached patch in #175092 (using `GetTriple().getArch()` with `std::unique_ptr`), along with the unit tests. I've also addressed your inline suggestions on the test comments. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 704f3f099f10aefd96bc5802cf0c5e7975e311da Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Thu, 15 Jan 2026 02:38:41 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 22 +++
.../Instruction/RISCV/TestRISCVEmulator.cpp | 17 ++
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..960261a83355c 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,8 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoInterface.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,10 +1839,22 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ std::unique_ptr reg_info;
+ switch (m_arch.GetTriple().getArch()) {
+ case llvm::Triple::riscv32:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+break;
+ case llvm::Triple::riscv64:
+reg_info = std::make_unique(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
+break;
+ default:
+return {};
+ }
+
+ const RegisterInfo *array = reg_info->GetRegisterInfo();
+ const uint32_t length = reg_info->GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..f713755c77a7c 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,19 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for riscv64.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for riscv32.
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
JDevlieghere wrote: > @JDevlieghere could you help get this PR merged so I can move on to > contributing to other issues? Similar to David's earlier comment, repeatedly asking for your PR to get merged is having the opposite effect. Reviewer bandwidth is limited, so please be mindful of that. You're free to start working on another issue while this PR is going through the review process. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
@@ -806,3 +807,21 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for RV64
JDevlieghere wrote:
```suggestion
// Test that GetRegisterInfo returns valid register info for riscv64.
```
https://github.com/llvm/llvm-project/pull/175262
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
@@ -806,3 +807,21 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for RV64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for RV32
+ // This verifies the fix for issue #175092 where GetRegisterInfo was
+ // hardcoded to use RegisterInfoPOSIX_riscv64
JDevlieghere wrote:
Testing the desired behavior is sufficient. We can use git blame to figure out
why the test was added if anyone wants to find out.
```suggestion
// Test that GetRegisterInfo returns valid register info for riscv32.
```
https://github.com/llvm/llvm-project/pull/175262
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
MkDev11 wrote: @JDevlieghere could you help get this PR merged so I can move on to contributing to other issues? https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
@@ -1837,15 +1851,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
-
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv32(m_arch,
+ RegisterInfoPOSIX_riscv32::eRegsetMaskAll),
+reg_index, reg_kind);
+ default:
MkDev11 wrote:
Done, could you please review the changes again?
https://github.com/llvm/llvm-project/pull/175262
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 021bda28a839b1f7f719eb63fe3301e1d9971313 Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Thu, 15 Jan 2026 02:38:41 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 36 ++-
.../Instruction/RISCV/TestRISCVEmulator.cpp | 19 ++
2 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..d9f8d97ef9e4f 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1809,6 +1810,19 @@ bool EmulateInstructionRISCV::SetAccruedExceptions(
return WriteRegisterUnsigned(ctx, eRegisterKindLLDB, fpr_fcsr_riscv, fcsr);
}
+template
+static std::optional
+GetRegisterInfoHelper(const T ®_info, uint32_t reg_index,
+ RegisterKind reg_kind) {
+ const RegisterInfo *array = reg_info.GetRegisterInfo();
+ const uint32_t length = reg_info.GetRegisterCount();
+
+ if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+return {};
+
+ return array[reg_index];
+}
+
std::optional
EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
uint32_t reg_index) {
@@ -1837,15 +1851,19 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
-
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv32(m_arch,
+ RegisterInfoPOSIX_riscv32::eRegsetMaskAll),
+reg_index, reg_kind);
+ case ArchSpec::eCore_riscv64:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv64(m_arch,
+ RegisterInfoPOSIX_riscv64::eRegsetMaskAll),
+reg_index, reg_kind);
+ }
+ llvm_unreachable("unsupported architecture");
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..39b07f7ec76a6 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,21 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for RV64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for RV32
+ // This verifies the fix for issue #175092 where GetRegisterInfo was
+ // hardcoded to use RegisterInfoPOSIX_riscv64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/JDevlieghere requested changes to this pull request. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
@@ -1837,15 +1851,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
-
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv32(m_arch,
+ RegisterInfoPOSIX_riscv32::eRegsetMaskAll),
+reg_index, reg_kind);
+ default:
JDevlieghere wrote:
I would prefer to handle `eCore_riscv32` and `eCore_riscv64` explicitly, omit
the `default` case and instead use an unreachable to make it clear that only
those two are supported.
https://github.com/llvm/llvm-project/pull/175262
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
MkDev11 wrote: @adrian-prantl is it impossible for you to merge the PR? https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 7fa5bc6e59b113a3de6a7ac7055b046410896c8c Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Mon, 12 Jan 2026 15:46:56 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 35 ++-
.../Instruction/RISCV/TestRISCVEmulator.cpp | 19 ++
2 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..a12b78b0cd803 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1809,6 +1810,19 @@ bool EmulateInstructionRISCV::SetAccruedExceptions(
return WriteRegisterUnsigned(ctx, eRegisterKindLLDB, fpr_fcsr_riscv, fcsr);
}
+template
+static std::optional
+GetRegisterInfoHelper(const T ®_info, uint32_t reg_index,
+ RegisterKind reg_kind) {
+ const RegisterInfo *array = reg_info.GetRegisterInfo();
+ const uint32_t length = reg_info.GetRegisterCount();
+
+ if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+return {};
+
+ return array[reg_index];
+}
+
std::optional
EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
uint32_t reg_index) {
@@ -1837,15 +1851,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
-
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv32(m_arch,
+ RegisterInfoPOSIX_riscv32::eRegsetMaskAll),
+reg_index, reg_kind);
+ default:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv64(m_arch,
+ RegisterInfoPOSIX_riscv64::eRegsetMaskAll),
+reg_index, reg_kind);
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..39b07f7ec76a6 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,21 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for RV64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for RV32
+ // This verifies the fix for issue #175092 where GetRegisterInfo was
+ // hardcoded to use RegisterInfoPOSIX_riscv64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/adrian-prantl approved this pull request. I am not familiar with this plugin, but from what I can tell, this looks like a reasonable change to me. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
DavidSpickett wrote: Pinging random people is not going to get your code reviewed any faster, much the opposite in fact. It is customary to wait a week before pinging anyone, as noted in the comment above. We are all busy people and doubly so around this time of year. Jonas will get to this when they have time. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 7fa5bc6e59b113a3de6a7ac7055b046410896c8c Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Mon, 12 Jan 2026 15:46:56 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 35 ++-
.../Instruction/RISCV/TestRISCVEmulator.cpp | 19 ++
2 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..a12b78b0cd803 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1809,6 +1810,19 @@ bool EmulateInstructionRISCV::SetAccruedExceptions(
return WriteRegisterUnsigned(ctx, eRegisterKindLLDB, fpr_fcsr_riscv, fcsr);
}
+template
+static std::optional
+GetRegisterInfoHelper(const T ®_info, uint32_t reg_index,
+ RegisterKind reg_kind) {
+ const RegisterInfo *array = reg_info.GetRegisterInfo();
+ const uint32_t length = reg_info.GetRegisterCount();
+
+ if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+return {};
+
+ return array[reg_index];
+}
+
std::optional
EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
uint32_t reg_index) {
@@ -1837,15 +1851,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
-
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv32(m_arch,
+ RegisterInfoPOSIX_riscv32::eRegsetMaskAll),
+reg_index, reg_kind);
+ default:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv64(m_arch,
+ RegisterInfoPOSIX_riscv64::eRegsetMaskAll),
+reg_index, reg_kind);
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..39b07f7ec76a6 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,21 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for RV64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for RV32
+ // This verifies the fix for issue #175092 where GetRegisterInfo was
+ // hardcoded to use RegisterInfoPOSIX_riscv64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
MkDev11 wrote: @AaronBallman can you please review the changes and let me know your feedback? it's been 4 days since I created the PR and would like to make this merge asap :) https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 7fa5bc6e59b113a3de6a7ac7055b046410896c8c Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Mon, 12 Jan 2026 15:46:56 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 35 ++-
.../Instruction/RISCV/TestRISCVEmulator.cpp | 19 ++
2 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..a12b78b0cd803 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1809,6 +1810,19 @@ bool EmulateInstructionRISCV::SetAccruedExceptions(
return WriteRegisterUnsigned(ctx, eRegisterKindLLDB, fpr_fcsr_riscv, fcsr);
}
+template
+static std::optional
+GetRegisterInfoHelper(const T ®_info, uint32_t reg_index,
+ RegisterKind reg_kind) {
+ const RegisterInfo *array = reg_info.GetRegisterInfo();
+ const uint32_t length = reg_info.GetRegisterCount();
+
+ if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+return {};
+
+ return array[reg_index];
+}
+
std::optional
EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
uint32_t reg_index) {
@@ -1837,15 +1851,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
-
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv32(m_arch,
+ RegisterInfoPOSIX_riscv32::eRegsetMaskAll),
+reg_index, reg_kind);
+ default:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv64(m_arch,
+ RegisterInfoPOSIX_riscv64::eRegsetMaskAll),
+reg_index, reg_kind);
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..39b07f7ec76a6 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,21 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for RV64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for RV32
+ // This verifies the fix for issue #175092 where GetRegisterInfo was
+ // hardcoded to use RegisterInfoPOSIX_riscv64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
MkDev11 wrote: @JDevlieghere can you please review the changes and let me know your feedback? it's been 4 days since I created the PR and would like to make this merge asap :) https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 7fa5bc6e59b113a3de6a7ac7055b046410896c8c Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Mon, 12 Jan 2026 15:46:56 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 35 ++-
.../Instruction/RISCV/TestRISCVEmulator.cpp | 19 ++
2 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..a12b78b0cd803 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1809,6 +1810,19 @@ bool EmulateInstructionRISCV::SetAccruedExceptions(
return WriteRegisterUnsigned(ctx, eRegisterKindLLDB, fpr_fcsr_riscv, fcsr);
}
+template
+static std::optional
+GetRegisterInfoHelper(const T ®_info, uint32_t reg_index,
+ RegisterKind reg_kind) {
+ const RegisterInfo *array = reg_info.GetRegisterInfo();
+ const uint32_t length = reg_info.GetRegisterCount();
+
+ if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+return {};
+
+ return array[reg_index];
+}
+
std::optional
EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
uint32_t reg_index) {
@@ -1837,15 +1851,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
-
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv32(m_arch,
+ RegisterInfoPOSIX_riscv32::eRegsetMaskAll),
+reg_index, reg_kind);
+ default:
+return GetRegisterInfoHelper(
+RegisterInfoPOSIX_riscv64(m_arch,
+ RegisterInfoPOSIX_riscv64::eRegsetMaskAll),
+reg_index, reg_kind);
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..39b07f7ec76a6 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,21 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for RV64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for RV32
+ // This verifies the fix for issue #175092 where GetRegisterInfo was
+ // hardcoded to use RegisterInfoPOSIX_riscv64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
___
lldb-commits mailing list
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From a49feb795c912d9c4a0b28cc17be15489b88f1da Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Mon, 12 Jan 2026 15:46:56 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 26 ++-
.../Instruction/RISCV/TestRISCVEmulator.cpp | 19 ++
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..f0e21b8585bb2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,15 +1838,26 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ auto get_register_info_helper =
+ [reg_index,
+ reg_kind](const auto ®_info) -> std::optional {
+const RegisterInfo *array = reg_info.GetRegisterInfo();
+const uint32_t length = reg_info.GetRegisterCount();
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
+if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+ return {};
+
+return array[reg_index];
+ };
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return get_register_info_helper(RegisterInfoPOSIX_riscv32(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll));
+ default:
+return get_register_info_helper(RegisterInfoPOSIX_riscv64(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll));
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 90d5a7c4f3b97..39b07f7ec76a6 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@@ -806,3 +807,21 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
+
+TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
+ // Test that GetRegisterInfo returns valid register info for RV64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 8u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
+
+TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
+ // Test that GetRegisterInfo returns valid register info for RV32
+ // This verifies the fix for issue #175092 where GetRegisterInfo was
+ // hardcoded to use RegisterInfoPOSIX_riscv64
+ auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
+ ASSERT_TRUE(reg_info.has_value());
+ ASSERT_EQ(reg_info->byte_size, 4u);
+ ASSERT_STREQ(reg_info->name, "ra");
+}
___
lldb-commits mailing list
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From c851762bb1c69566dcee36d517d0baac169cee47 Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Mon, 12 Jan 2026 15:46:56 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../RISCV/EmulateInstructionRISCV.cpp | 26 ++-
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..f0e21b8585bb2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,15 +1838,26 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
+ auto get_register_info_helper =
+ [reg_index,
+ reg_kind](const auto ®_info) -> std::optional {
+const RegisterInfo *array = reg_info.GetRegisterInfo();
+const uint32_t length = reg_info.GetRegisterCount();
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
+if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+ return {};
+
+return array[reg_index];
+ };
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return get_register_info_helper(RegisterInfoPOSIX_riscv32(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll));
+ default:
+return get_register_info_helper(RegisterInfoPOSIX_riscv64(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll));
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 591b85b1d93df16eef1011b921fb2d793e64e4de Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sat, 10 Jan 2026 00:41:01 +0200
Subject: [PATCH 1/2] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../Instruction/RISCV/EmulateInstructionRISCV.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..76016e4dd7cb6 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,6 +1838,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
+ if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
+RegisterInfoPOSIX_riscv32 reg_info(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+const RegisterInfo *array = reg_info.GetRegisterInfo();
+uint32_t length = reg_info.GetRegisterCount();
+
+if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+ return {};
+
+return array[reg_index];
+ }
+
RegisterInfoPOSIX_riscv64 reg_info(m_arch,
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
const RegisterInfo *array = reg_info.GetRegisterInfo();
>From b3a6e4392f191b9f3d17a7eb9f837d1009d20930 Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sun, 11 Jan 2026 22:42:51 +0200
Subject: [PATCH 2/2] Refactor GetRegisterInfo to reduce code duplication
Address review feedback by using a lambda helper function instead of
duplicating the register info retrieval logic for both RISCV-32 and
RISCV-64.
---
.../RISCV/EmulateInstructionRISCV.cpp | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 76016e4dd7cb6..f0e21b8585bb2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -1838,27 +1838,26 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
-RegisterInfoPOSIX_riscv32 reg_info(
-m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+ auto get_register_info_helper =
+ [reg_index,
+ reg_kind](const auto ®_info) -> std::optional {
const RegisterInfo *array = reg_info.GetRegisterInfo();
-uint32_t length = reg_info.GetRegisterCount();
+const uint32_t length = reg_info.GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
return array[reg_index];
- }
-
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
+ };
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return get_register_info_helper(RegisterInfoPOSIX_riscv32(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll));
+ default:
+return get_register_info_helper(RegisterInfoPOSIX_riscv64(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll));
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
MkDev11 wrote: done! can please review the changes and let me know your feedback again? https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 591b85b1d93df16eef1011b921fb2d793e64e4de Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sat, 10 Jan 2026 00:41:01 +0200
Subject: [PATCH 1/2] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../Instruction/RISCV/EmulateInstructionRISCV.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..76016e4dd7cb6 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,6 +1838,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
+ if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
+RegisterInfoPOSIX_riscv32 reg_info(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+const RegisterInfo *array = reg_info.GetRegisterInfo();
+uint32_t length = reg_info.GetRegisterCount();
+
+if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+ return {};
+
+return array[reg_index];
+ }
+
RegisterInfoPOSIX_riscv64 reg_info(m_arch,
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
const RegisterInfo *array = reg_info.GetRegisterInfo();
>From b3a6e4392f191b9f3d17a7eb9f837d1009d20930 Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sun, 11 Jan 2026 22:42:51 +0200
Subject: [PATCH 2/2] Refactor GetRegisterInfo to reduce code duplication
Address review feedback by using a lambda helper function instead of
duplicating the register info retrieval logic for both RISCV-32 and
RISCV-64.
---
.../RISCV/EmulateInstructionRISCV.cpp | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 76016e4dd7cb6..f0e21b8585bb2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -1838,27 +1838,26 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
-RegisterInfoPOSIX_riscv32 reg_info(
-m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+ auto get_register_info_helper =
+ [reg_index,
+ reg_kind](const auto ®_info) -> std::optional {
const RegisterInfo *array = reg_info.GetRegisterInfo();
-uint32_t length = reg_info.GetRegisterCount();
+const uint32_t length = reg_info.GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
return array[reg_index];
- }
-
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
+ };
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return get_register_info_helper(RegisterInfoPOSIX_riscv32(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll));
+ default:
+return get_register_info_helper(RegisterInfoPOSIX_riscv64(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll));
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 591b85b1d93df16eef1011b921fb2d793e64e4de Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sat, 10 Jan 2026 00:41:01 +0200
Subject: [PATCH 1/2] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../Instruction/RISCV/EmulateInstructionRISCV.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..76016e4dd7cb6 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,6 +1838,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
+ if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
+RegisterInfoPOSIX_riscv32 reg_info(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+const RegisterInfo *array = reg_info.GetRegisterInfo();
+uint32_t length = reg_info.GetRegisterCount();
+
+if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+ return {};
+
+return array[reg_index];
+ }
+
RegisterInfoPOSIX_riscv64 reg_info(m_arch,
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
const RegisterInfo *array = reg_info.GetRegisterInfo();
>From b3a6e4392f191b9f3d17a7eb9f837d1009d20930 Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sun, 11 Jan 2026 22:42:51 +0200
Subject: [PATCH 2/2] Refactor GetRegisterInfo to reduce code duplication
Address review feedback by using a lambda helper function instead of
duplicating the register info retrieval logic for both RISCV-32 and
RISCV-64.
---
.../RISCV/EmulateInstructionRISCV.cpp | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 76016e4dd7cb6..f0e21b8585bb2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -1838,27 +1838,26 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
- if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
-RegisterInfoPOSIX_riscv32 reg_info(
-m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+ auto get_register_info_helper =
+ [reg_index,
+ reg_kind](const auto ®_info) -> std::optional {
const RegisterInfo *array = reg_info.GetRegisterInfo();
-uint32_t length = reg_info.GetRegisterCount();
+const uint32_t length = reg_info.GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
return array[reg_index];
- }
-
- RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
- const RegisterInfo *array = reg_info.GetRegisterInfo();
- const uint32_t length = reg_info.GetRegisterCount();
-
- if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-return {};
+ };
- return array[reg_index];
+ switch (m_arch.GetCore()) {
+ case ArchSpec::eCore_riscv32:
+return get_register_info_helper(RegisterInfoPOSIX_riscv32(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll));
+ default:
+return get_register_info_helper(RegisterInfoPOSIX_riscv64(
+m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll));
+ }
}
bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
JDevlieghere wrote:
The logic looks good, but there's a lot of unnecessary code duplication. The
common base class is abstract, so maybe a templated static helper is the answer:
```
template
GetRegisterInfo(const T& reg_info, reg_index, reg_kind) {
const RegisterInfo *array = reg_info.GetRegisterInfo();
const uint32_t length = reg_info.GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
return array[reg_index];
}
```
and then switch on `m_arch.GetCore()`
```
switch(m_arch.GetCore()) {
case ArchSpec::eCore_riscv32
return GetRegisterInfo(RegisterInfoPOSIX_riscv32(...), reg_index, reg_kind);
...
}
```
https://github.com/llvm/llvm-project/pull/175262
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 591b85b1d93df16eef1011b921fb2d793e64e4de Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sat, 10 Jan 2026 00:41:01 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../Instruction/RISCV/EmulateInstructionRISCV.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..76016e4dd7cb6 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,6 +1838,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
+ if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
+RegisterInfoPOSIX_riscv32 reg_info(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+const RegisterInfo *array = reg_info.GetRegisterInfo();
+uint32_t length = reg_info.GetRegisterCount();
+
+if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+ return {};
+
+return array[reg_index];
+ }
+
RegisterInfoPOSIX_riscv64 reg_info(m_arch,
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
const RegisterInfo *array = reg_info.GetRegisterInfo();
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 591b85b1d93df16eef1011b921fb2d793e64e4de Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sat, 10 Jan 2026 00:41:01 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../Instruction/RISCV/EmulateInstructionRISCV.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..76016e4dd7cb6 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,6 +1838,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
+ if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
+RegisterInfoPOSIX_riscv32 reg_info(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+const RegisterInfo *array = reg_info.GetRegisterInfo();
+uint32_t length = reg_info.GetRegisterCount();
+
+if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+ return {};
+
+return array[reg_index];
+ }
+
RegisterInfoPOSIX_riscv64 reg_info(m_arch,
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
const RegisterInfo *array = reg_info.GetRegisterInfo();
___
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
https://github.com/MkDev11 updated
https://github.com/llvm/llvm-project/pull/175262
>From 591b85b1d93df16eef1011b921fb2d793e64e4de Mon Sep 17 00:00:00 2001
From: mkdev11
Date: Sat, 10 Jan 2026 00:41:01 +0200
Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32
GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.
This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.
Fixes #175092
---
.../Instruction/RISCV/EmulateInstructionRISCV.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..76016e4dd7cb6 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@@ -1837,6 +1838,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind
reg_kind,
}
}
+ if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
+RegisterInfoPOSIX_riscv32 reg_info(
+m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+const RegisterInfo *array = reg_info.GetRegisterInfo();
+uint32_t length = reg_info.GetRegisterCount();
+
+if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+ return {};
+
+return array[reg_index];
+ }
+
RegisterInfoPOSIX_riscv64 reg_info(m_arch,
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
const RegisterInfo *array = reg_info.GetRegisterInfo();
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[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)
jasilvanus wrote: Did you intentionally ping me? I don't think I've ever worked on lldb or RISCV. https://github.com/llvm/llvm-project/pull/175262 ___ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
