[llvm-branch-commits] [clang] [Serialization] No transitive identifier change (PR #92085)

https://github.com/ChuanqiXu9 updated https://github.com/llvm/llvm-project/pull/92085 >From c612b56dec8bfc7c1612e94be8876316f14ea8ea Mon Sep 17 00:00:00 2001 From: Chuanqi Xu Date: Tue, 14 May 2024 15:33:12 +0800 Subject: [PATCH] [Serialization] No transitive identifier change --- .../clang/L

[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)

@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) { ret <4 x i32> %sel } +define i32 @pr91691(i32 %0) { +; CHECK-LABEL: @pr91691( +; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]] +; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32 @llv

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

nikic wrote: @topperc Yes, it has been changed back for LLVM 19. See https://github.com/rust-lang/rust/blob/8387315ab3c26a57a1f53a90f188f0bc88514bca/compiler/rustc_codegen_llvm/src/llvm_util.rs#L273-L277 https://github.com/llvm/llvm-project/pull/92143 ___

[llvm-branch-commits] [llvm] 8d8432d - Revert "[ctx_profile] Profile reader and writer (#91859)"

Author: Mircea Trofin Date: 2024-05-14T18:07:38-07:00 New Revision: 8d8432d158ca1cb8a138e1cee4d48f23ba9d4c64 URL: https://github.com/llvm/llvm-project/commit/8d8432d158ca1cb8a138e1cee4d48f23ba9d4c64 DIFF: https://github.com/llvm/llvm-project/commit/8d8432d158ca1cb8a138e1cee4d48f23ba9d4c64.diff

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > > Note that backporting this may require changes for LLVM users (I know that > > it will require rustc changes at least). This may not be a good candidate > > for the last 18.1 point release. > > Can you point me to the relevant rust code? I found this line which looks > like

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > Note that backporting this may require changes for LLVM users (I know that it > will require rustc changes at least). This may not be a good candidate for > the last 18.1 point release. Can you point me to the relevant rust code? I found this line which looks like it wasn't u

[llvm-branch-commits] [llvm] release/18.x: [LV, LAA] Don't vectorize loops with load and store to invar address. (PR #91092)

nikic wrote: The size of the structure doesn't change, but the initialization requirements and the meaning of the members do. Given that this doesn't seem to address any real-world issue, I think it's safer not to backport this into the last 18.1 point release. https://github.com/llvm/llvm-pr

[llvm-branch-commits] [llvm] [AArch64][PAC] Lower authenticated calls with ptrauth bundles. (PR #85736)

https://github.com/ahmedbougacha updated https://github.com/llvm/llvm-project/pull/85736 >From 75825f36ec58a2cf5d1a3f2d4de6a49ad06c02d8 Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha Date: Mon, 27 Sep 2021 08:00:00 -0700 Subject: [PATCH 1/2] [AArch64] Adopt x8+ allocation order for GPR64noip. 7

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

nikic wrote: Note that backporting this may require changes for LLVM users (I know that it will require rustc changes at least). This may not be a good candidate for the last 18.1 point release. https://github.com/llvm/llvm-project/pull/92143 ___ llv

[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)

nikic wrote: This is probably more of a question for @alexey-bataev. https://github.com/llvm/llvm-project/pull/91682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-com

[llvm-branch-commits] [libcxx] release/18.x: change the visibility of libc++ header to public in libcxx module (PR #91182)

tstellar wrote: @mordante Do you think we should backport this? https://github.com/llvm/llvm-project/pull/91182 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)

tstellar wrote: @AtariDreams (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://

[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91419 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 494847b - [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215)

Author: Yingwei Zheng Date: 2024-05-14T16:32:24-07:00 New Revision: 494847ba8fef9a29cfa92aac3f8aaa1102b5d44f URL: https://github.com/llvm/llvm-project/commit/494847ba8fef9a29cfa92aac3f8aaa1102b5d44f DIFF: https://github.com/llvm/llvm-project/commit/494847ba8fef9a29cfa92aac3f8aaa1102b5d44f.diff

[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/91419 >From 494847ba8fef9a29cfa92aac3f8aaa1102b5d44f Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 8 May 2024 10:04:09 +0800 Subject: [PATCH] [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced

[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] fac122a - [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694)

Author: Phoebe Wang Date: 2024-05-14T16:26:16-07:00 New Revision: fac122ac439191d5f46da6400681c54b0bf7e3db URL: https://github.com/llvm/llvm-project/commit/fac122ac439191d5f46da6400681c54b0bf7e3db DIFF: https://github.com/llvm/llvm-project/commit/fac122ac439191d5f46da6400681c54b0bf7e3db.diff L

[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/91705 >From fac122ac439191d5f46da6400681c54b0bf7e3db Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Fri, 10 May 2024 13:25:37 +0800 Subject: [PATCH] [X86][Driver] Do not add `-evex512` for `-march=native` when the

[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)

tstellar wrote: @phoebewang (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://g

[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] 38c3588 - Revert "Read and store gnu build id from loaded core file (#92078)"

Author: GeorgeHuyubo Date: 2024-05-14T14:35:56-07:00 New Revision: 38c358868dfb6d22c7e27032ad910c9f4e61092f URL: https://github.com/llvm/llvm-project/commit/38c358868dfb6d22c7e27032ad910c9f4e61092f DIFF: https://github.com/llvm/llvm-project/commit/38c358868dfb6d22c7e27032ad910c9f4e61092f.diff

[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)

AtariDreams wrote: Fixed issue where incorrect code is generated on AArch64 when the source code has multiple different comparisons with the same two values. https://github.com/llvm/llvm-project/pull/91151 ___ llvm-branch-commits mailing list llvm-bra

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

tstellar wrote: Hi @topperc (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://gi

[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/91419 >From 0a5378ecdc47e357a0c1b8631e583ba12ad6e3b0 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 8 May 2024 10:04:09 +0800 Subject: [PATCH] [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced

[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)

tstellar wrote: @AtariDreams (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://g

[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91151 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 47b6dc4 - [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911)

Author: Weihang Fan Date: 2024-05-14T14:13:35-07:00 New Revision: 47b6dc45e39aea5369308c602f0d6341a054aca2 URL: https://github.com/llvm/llvm-project/commit/47b6dc45e39aea5369308c602f0d6341a054aca2 DIFF: https://github.com/llvm/llvm-project/commit/47b6dc45e39aea5369308c602f0d6341a054aca2.diff L

[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/91151 >From 47b6dc45e39aea5369308c602f0d6341a054aca2 Mon Sep 17 00:00:00 2001 From: Weihang Fan <134108011+weihangf-ap...@users.noreply.github.com> Date: Sun, 5 May 2024 04:01:13 -0700 Subject: [PATCH] [AArch64][Select

[llvm-branch-commits] [clang] be23965 - [RISCV] Add canonical ISA string as Module metadata in IR. (#80760)

Author: Craig Topper Date: 2024-05-14T12:58:46-07:00 New Revision: be239653149f45e4a23036c840ae0bcdc9818161 URL: https://github.com/llvm/llvm-project/commit/be239653149f45e4a23036c840ae0bcdc9818161 DIFF: https://github.com/llvm/llvm-project/commit/be239653149f45e4a23036c840ae0bcdc9818161.diff

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91514 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] dff7178 - [RISCV] Use 'riscv-isa' module flag to set ELF flags and attributes. (#85155)

Author: Craig Topper Date: 2024-05-14T12:58:46-07:00 New Revision: dff7178183567f1f2a9ad1e2eb99da9fae019e15 URL: https://github.com/llvm/llvm-project/commit/dff7178183567f1f2a9ad1e2eb99da9fae019e15 DIFF: https://github.com/llvm/llvm-project/commit/dff7178183567f1f2a9ad1e2eb99da9fae019e15.diff

[llvm-branch-commits] [llvm] 3512b12 - [RISCV] Store RVC and TSO ELF flags explicitly in RISCVTargetStreamer. NFCI (#83344)

Author: Craig Topper Date: 2024-05-14T12:58:46-07:00 New Revision: 3512b12a79818b8089fcfa223586981a15ffb6b4 URL: https://github.com/llvm/llvm-project/commit/3512b12a79818b8089fcfa223586981a15ffb6b4 DIFF: https://github.com/llvm/llvm-project/commit/3512b12a79818b8089fcfa223586981a15ffb6b4.diff

[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/91514 >From be239653149f45e4a23036c840ae0bcdc9818161 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 13 Feb 2024 16:17:50 -0800 Subject: [PATCH 1/3] [RISCV] Add canonical ISA string as Module metadata in IR. (

[llvm-branch-commits] [llvm] [CallPromotionUtils]Implement conditional indirect call promotion with vtable-based comparison (PR #81378)

https://github.com/minglotus-6 edited https://github.com/llvm/llvm-project/pull/81378 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) Changes Backport 9067070d91e9d8cdd8509ffa56a076f08a3d7281 for #92134 --- Patch is 21.98 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/92143.diff 21 Files Affe

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/92143 Backport 9067070d91e9d8cdd8509ffa56a076f08a3d7281 for #92134 >From 5c5c57534751621f775dca5776af10e1870e6eb8 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 16 Apr 2024 15:40:32 -0700 Subject: [PATCH] [RIS

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc milestoned https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [workflows] Rework pre-commit CI for the release branch (PR #91550)

tstellar wrote: This PR is for testing purposes only, the main PR is here: #92058 https://github.com/llvm/llvm-project/pull/91550 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/ll

[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)

@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) { ret <4 x i32> %sel } +define i32 @pr91691(i32 %0) { +; CHECK-LABEL: @pr91691( +; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]] +; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32 @llv

[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: None (llvmbot) Changes Backport d422e90fcb68749918ddd86c94188807efce Requested by: @DianQK --- Full diff: https://github.com/llvm/llvm-project/pull/92129.diff 2 Files Affected: - (modified) llvm/lib/Target/AArch64/GISel/A

[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)

llvmbot wrote: @DianQK What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinf

[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/92129 Backport d422e90fcb68749918ddd86c94188807efce Requested by: @DianQK >From 273eaada783556afddbcbdbbf1b3399d73de5343 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Tue, 14 May 2024 15

[llvm-branch-commits] [clang] [clang] Revise IDE folder structure (PR #89743)

AaronBallman wrote: > @AaronBallman Thanks for having a look. > > > With this patch, I get errors when loading a visual studio solution > > generated with these change, and all of clang's libraries are placed at the > > top level. The error is a dialog box saying "The solution already contains

[llvm-branch-commits] [clang] [flang] [llvm] [openmp] [Clang][OpenMP] Add reverse and interchange directives (PR #92030)

@@ -15745,6 +15760,388 @@ StmtResult SemaOpenMP::ActOnOpenMPUnrollDirective(ArrayRef Clauses, buildPreInits(Context, PreInits)); } +StmtResult +SemaOpenMP::ActOnOpenMPReverseDirective(ArrayRef Clauses, +

[llvm-branch-commits] [clang] [flang] [llvm] [openmp] [Clang][OpenMP] Add reverse and interchange directives (PR #92030)

@@ -15745,6 +15760,388 @@ StmtResult SemaOpenMP::ActOnOpenMPUnrollDirective(ArrayRef Clauses, buildPreInits(Context, PreInits)); } +StmtResult +SemaOpenMP::ActOnOpenMPReverseDirective(ArrayRef Clauses, +

[llvm-branch-commits] [clang] [flang] [llvm] [openmp] [Clang][OpenMP] Add reverse and interchange directives (PR #92030)

@@ -870,6 +870,106 @@ class OMPSizesClause final } }; +/// This class represents the 'permutation' clause in the +/// '#pragma omp interchange' directive. +/// +/// \code{c} +/// #pragma omp interchange permutation(2,1) +/// for (int i = 0; i < 64; ++i) +/// for (int

[llvm-branch-commits] [clang] [flang] [llvm] [openmp] [Clang][OpenMP] Add reverse and interchange directives (PR #92030)

@@ -2146,6 +2146,14 @@ enum CXCursorKind { */ CXCursor_OMPScopeDirective = 306, + /** OpenMP reverse directive. + */ + CXCursor_OMPReverseDirective = 307, + alexey-bataev wrote: Split this into 2 patches, one for reverse, one for interchange https:/

[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)

davemgreen wrote: LGTM, I believe this should be safe to merge, if there are people asking for it. https://github.com/llvm/llvm-project/pull/91151 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/ma

[llvm-branch-commits] [clang] [Serialization] No transitive identifier change (PR #92085)

llvmbot wrote: @llvm/pr-subscribers-clang-modules Author: Chuanqi Xu (ChuanqiXu9) Changes Following of https://github.com/llvm/llvm-project/pull/92083 The motivation is still cutting of the unnecessary change in the dependency chain. See the above link (recursively) for details. After t

[llvm-branch-commits] [clang] [Serialization] No transitive identifier change (PR #92085)

https://github.com/ChuanqiXu9 created https://github.com/llvm/llvm-project/pull/92085 Following of https://github.com/llvm/llvm-project/pull/92083 The motivation is still cutting of the unnecessary change in the dependency chain. See the above link (recursively) for details. After this patch,