ivanradanov wrote:
I have rebased this on the latest main and also marked the follow up
https://github.com/llvm/llvm-project/pull/104748 as ready for review. This
follow up PR contains code and tests which are needed to fully check this
implementation as well.
I think this stack is currently
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/112730
>From 5e460594c8a2550c38c759b2e6f1c5dc4152f820 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Thu, 17 Oct 2024 22:15:12 +0900
Subject: [PATCH 1/2] [Coverage] Make additional counters available for
BranchR
boomanaiden154 wrote:
> IIRC we have several lit tests that cover structural hash, shouldn't we have
> a new test there that uses the new functionality?
The lit tests for structural hashing are pretty limited and mostly designed to
just test the structural hash printer pass that I needed for o
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
llvmbot wrote:
@zygoloid What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/113052
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@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (llvmbot)
Changes
Backport 76196998e25b98d81abc437708622261810782ca
Requested by: @mgorny
---
Full diff: https://github.com/llvm/llvm-project/pull/113052.diff
1 Files Affected:
- (modified) clang/include/clang/AST/ExternalASTSourc
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
---
kyulee-com wrote:
The test failure `TableGen/x86-fold-tables.td` seems unrelated.
https://github.com/llvm/llvm-project/pull/112638
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@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
https://github.com/tschuett edited
https://github.com/llvm/llvm-project/pull/112863
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@@ -100,8 +233,20 @@ class StructuralHashImpl {
if (const auto *ComparisonInstruction = dyn_cast(&Inst))
Hashes.emplace_back(ComparisonInstruction->getPredicate());
-for (const auto &Op : Inst.operands())
- Hashes.emplace_back(hashOperand(Op));
+unsigned
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/113052
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https://github.com/ivanradanov updated
https://github.com/llvm/llvm-project/pull/101445
>From 6f114e0501f1759eab34dc8ddfc3030c03037cd4 Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov
Date: Thu, 22 Aug 2024 18:07:05 +0900
Subject: [PATCH 1/2] [flang] Introduce ws loop nest generation for HLFI
https://github.com/ivanradanov updated
https://github.com/llvm/llvm-project/pull/101444
>From bf363883787e9b4989dd858f8573579688f7044b Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov
Date: Wed, 31 Jul 2024 14:11:47 +0900
Subject: [PATCH 1/2] [flang][omp] Emit omp.workshare in frontend
Fix l
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/113052
Backport 76196998e25b98d81abc437708622261810782ca
Requested by: @mgorny
>From f062f8c06bb237ee79c098414eafe5eb075aa9c8 Mon Sep 17 00:00:00 2001
From: Jessica Clarke
Date: Fri, 18 Oct 2024 21:49:23 +0100
Subjec
@@ -47,24 +60,140 @@ class StructuralHashImpl {
public:
StructuralHashImpl() = delete;
- explicit StructuralHashImpl(bool DetailedHash) : DetailedHash(DetailedHash)
{}
+ explicit StructuralHashImpl(bool DetailedHash,
+ IgnoreOperandFunc Ignore
https://github.com/ivanradanov updated
https://github.com/llvm/llvm-project/pull/104748
>From 5aca24559fc6f64a06f66a6d7e35f1edc82995a5 Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov
Date: Sun, 4 Aug 2024 17:33:52 +0900
Subject: [PATCH 1/8] Add workshare loop wrapper lowerings
Bufferize tes
kyulee-com wrote:
> IIRC we have several lit tests that cover structural hash, shouldn't we have
> a new test there that uses the new functionality?
Extended the existing `StructuralHashPrinterPass` with `Options`, and updated
the corresponding lit test accordingly.
https://github.com/llvm/ll
https://github.com/ivanradanov ready_for_review
https://github.com/llvm/llvm-project/pull/104748
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>From 31ddd5c8bf59c4f6b386415c89bd87f80bb83409 Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov
Date: Wed, 31 Jul 2024 14:11:47 +0900
Subject: [PATCH 1/2] [flang][omp] Emit omp.workshare in frontend
Fix l
https://github.com/ivanradanov updated
https://github.com/llvm/llvm-project/pull/101446
>From cc9096e80fc62ba9c5a7d511ee7b8fd18750cb44 Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov
Date: Sun, 4 Aug 2024 22:06:55 +0900
Subject: [PATCH 01/14] [flang] Lower omp.workshare to other omp construc
https://github.com/ivanradanov updated
https://github.com/llvm/llvm-project/pull/101445
>From 159a2f46bf3a01322cb24539ede289ea089e62c6 Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov
Date: Thu, 22 Aug 2024 18:07:05 +0900
Subject: [PATCH 1/2] [flang] Introduce ws loop nest generation for HLFI
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -47,24 +60,140 @@ class StructuralHashImpl {
public:
StructuralHashImpl() = delete;
- explicit StructuralHashImpl(bool DetailedHash) : DetailedHash(DetailedHash)
{}
+ explicit StructuralHashImpl(bool DetailedHash,
+ IgnoreOperandFunc Ignore
@@ -47,24 +60,140 @@ class StructuralHashImpl {
public:
StructuralHashImpl() = delete;
- explicit StructuralHashImpl(bool DetailedHash) : DetailedHash(DetailedHash)
{}
+ explicit StructuralHashImpl(bool DetailedHash,
+ IgnoreOperandFunc Ignore
@@ -47,24 +60,140 @@ class StructuralHashImpl {
public:
StructuralHashImpl() = delete;
- explicit StructuralHashImpl(bool DetailedHash) : DetailedHash(DetailedHash)
{}
+ explicit StructuralHashImpl(bool DetailedHash,
+ IgnoreOperandFunc Ignore
@@ -47,24 +60,140 @@ class StructuralHashImpl {
public:
StructuralHashImpl() = delete;
- explicit StructuralHashImpl(bool DetailedHash) : DetailedHash(DetailedHash)
{}
+ explicit StructuralHashImpl(bool DetailedHash,
+ IgnoreOperandFunc Ignore
https://github.com/kyulee-com updated
https://github.com/llvm/llvm-project/pull/112638
>From 6225d74229d41068c57109a24b063f6fcba13985 Mon Sep 17 00:00:00 2001
From: Kyungwoo Lee
Date: Wed, 16 Oct 2024 17:09:07 -0700
Subject: [PATCH 1/3] [StructuralHash] Support Differences
This comutes a struc
@@ -409,32 +419,50 @@ class TypeConverter {
/// callback.
///
/// With callback of form:
- /// `Value(OpBuilder &, T, ValueRange, Location, Type)`
+ /// - Value(OpBuilder &, T, ValueRange, Location, Type)
+ /// - SmallVector(OpBuilder &, TypeRange, ValueRange, Location
@@ -409,32 +419,50 @@ class TypeConverter {
/// callback.
///
/// With callback of form:
- /// `Value(OpBuilder &, T, ValueRange, Location, Type)`
+ /// - Value(OpBuilder &, T, ValueRange, Location, Type)
+ /// - SmallVector(OpBuilder &, TypeRange, ValueRange, Location
@@ -293,7 +506,87 @@ RegBankLegalizeRules::RegBankLegalizeRules(const
GCNSubtarget &_ST,
.Any({{UniS64, S32}, {{Sgpr64}, {Sgpr32}, Ext32To64}})
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}, Ext32To64}});
- addRulesForGOpcs({G_LOAD}).Any({{DivS32, DivP1}, {{Vgpr32}, {
@@ -37,6 +37,97 @@ bool
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
return true;
}
+void RegBankLegalizeHelper::splitLoad(MachineInstr &MI,
+ ArrayRef LLTBreakdown, LLT MergeTy)
{
+ MachineFunction &MF = B.getMF(
@@ -119,6 +210,53 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
MI.eraseFromParent();
break;
}
+ case SplitLoad: {
+LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
+LLT V8S16 = LLT::fixed_vector(8, S16);
+LLT V4S32 = LLT::fixed_vector(4, S32)
@@ -236,6 +328,127 @@ RegBankLegalizeRules::getRulesForOpc(MachineInstr &MI)
const {
return GRules.at(GRulesAlias.at(Opc));
}
+// Syntactic sugar wrapper for predicate lambda that enables '&&', '||' and
'!'.
+class Predicate {
+public:
+ struct Elt {
+// Save formula
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -0,0 +1,334 @@
+//===-- AMDGPURBLegalizeRules.cpp
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -107,3 +107,183 @@ void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register
Reg) {
S32S64LaneMask.insert(LCSSAPhi.getOperand(0).getReg());
}
}
+
+MachineInstrBuilder AMDGPU::buildReadAnyLaneB32(MachineIRBuilder &B,
+const
@@ -0,0 +1,334 @@
+//===-- AMDGPURBLegalizeRules.cpp
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,258 @@
+//===- AMDGPURBLegalizeRules -*- C++
-*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -107,3 +107,183 @@ void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register
Reg) {
S32S64LaneMask.insert(LCSSAPhi.getOperand(0).getReg());
}
}
+
+MachineInstrBuilder AMDGPU::buildReadAnyLaneB32(MachineIRBuilder &B,
+const
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -107,3 +107,183 @@ void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register
Reg) {
S32S64LaneMask.insert(LCSSAPhi.getOperand(0).getReg());
}
}
+
+MachineInstrBuilder AMDGPU::buildReadAnyLaneB32(MachineIRBuilder &B,
+const
@@ -0,0 +1,118 @@
+//===- AMDGPURBLegalizeHelper *- C++
-*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -107,3 +107,183 @@ void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register
Reg) {
S32S64LaneMask.insert(LCSSAPhi.getOperand(0).getReg());
}
}
+
+MachineInstrBuilder AMDGPU::buildReadAnyLaneB32(MachineIRBuilder &B,
+const
@@ -69,3 +72,38 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI,
Register Reg,
return std::pair(Reg, 0);
}
+
+IntrinsicLaneMaskAnalyzer::IntrinsicLaneMaskAnalyzer(MachineFunction &MF)
+: MRI(MF.getRegInfo()) {
+ initLaneMaskIntrinsics(MF);
+}
+
+bool Intr
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/113038
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@@ -896,5 +896,6 @@ void test_set_fpenv(unsigned long env) {
__builtin_amdgcn_set_fpenv(env);
}
+// CHECK-DAG: [[$GRID_RANGE]] = !{i32 1, i32 0}
shiltian wrote:
oh I c. range does allow wrap.
https://github.com/llvm/llvm-project/pull/113038
___
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -69,3 +72,38 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI,
Register Reg,
return std::pair(Reg, 0);
}
+
+IntrinsicLaneMaskAnalyzer::IntrinsicLaneMaskAnalyzer(MachineFunction &MF)
+: MRI(MF.getRegInfo()) {
+ initLaneMaskIntrinsics(MF);
+}
+
+bool Intr
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/113038
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@@ -896,5 +896,6 @@ void test_set_fpenv(unsigned long env) {
__builtin_amdgcn_set_fpenv(env);
}
+// CHECK-DAG: [[$GRID_RANGE]] = !{i32 1, i32 0}
arsenm wrote:
Yes, this is how you are supposed to represent the wrapped set where the 0
value isn't allowed bu
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/112863
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https://github.com/arsenm commented:
Don't forget about AGPRs
https://github.com/llvm/llvm-project/pull/112863
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/113019
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@@ -896,5 +896,6 @@ void test_set_fpenv(unsigned long env) {
__builtin_amdgcn_set_fpenv(env);
}
+// CHECK-DAG: [[$GRID_RANGE]] = !{i32 1, i32 0}
shiltian wrote:
the upper bound is smaller than the lower bound?
https://github.com/llvm/llvm-project/pull/1130
https://github.com/ivanradanov updated
https://github.com/llvm/llvm-project/pull/101446
>From e56dbd6a0625890fd9a3d6a62675e864ca94a8f5 Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov
Date: Sun, 4 Aug 2024 22:06:55 +0900
Subject: [PATCH 01/13] [flang] Lower omp.workshare to other omp construc
https://github.com/ivanradanov updated
https://github.com/llvm/llvm-project/pull/104748
>From 4257950e7df8d7eaf92a1a7b02f89422007ffe6a Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov
Date: Sat, 19 Oct 2024 23:32:27 +0900
Subject: [PATCH 1/7] Do not emit empty omp.single's
---
flang/lib/Opt
https://github.com/heiher updated
https://github.com/llvm/llvm-project/pull/109093
>From bd494f3735df409fbe7360e98ff4d5cb55d4bf98 Mon Sep 17 00:00:00 2001
From: YANG Xudong
Date: Fri, 13 Sep 2024 08:49:54 +0800
Subject: [PATCH] [loongarch][DAG][FREEZE] Fix crash when FREEZE a half(f16)
type on
heiher wrote:
Update: https://github.com/llvm/llvm-project/pull/109368#issuecomment-2423879356
I suggest continuing this PR to ensure that fp16 support is functional on the
release/19.x.
https://github.com/llvm/llvm-project/pull/109093
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https://github.com/heiher reopened
https://github.com/llvm/llvm-project/pull/109093
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https://github.com/jhuber6 approved this pull request.
https://github.com/llvm/llvm-project/pull/113038
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
These cannot be 0.
---
Full diff: https://github.com/llvm/llvm-project/pull/113038.diff
2 Files Affected:
- (modified) clang/lib/CodeGen/CGBuiltin.cpp (+6)
- (modified) clang/test/CodeGenOpenCL/
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/113038
These cannot be 0.
>From 708215d0a144caafe7a9ebfbce5f8617c8215c49 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:39:06 +0400
Subject: [PATCH] clang/AMDGPU: Emit grid size builtins with r
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/113038?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/113038
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llvmbot wrote:
@llvm/pr-subscribers-mlir-sparse
Author: Matthias Springer (matthias-springer)
Changes
The 1:N type converter derived from the 1:1 type converter and extends it with
1:N target materializations. This commit merges the two type converters and
stores 1:N target materializati
https://github.com/matthias-springer updated
https://github.com/llvm/llvm-project/pull/113032
>From 7ac8aa2ee4ee5634d8dd6f2d64d0e10b800e2d70 Mon Sep 17 00:00:00 2001
From: Matthias Springer
Date: Sat, 19 Oct 2024 12:05:13 +0200
Subject: [PATCH] [mlir][Transforms] Merge 1:1 and 1:N type converte
llvmbot wrote:
@llvm/pr-subscribers-mlir
Author: Matthias Springer (matthias-springer)
Changes
The 1:N type converter derived from the 1:1 type converter and extends it with
1:N target materializations. This commit merges the two type converters and
stores 1:N target materializations in
llvmbot wrote:
@llvm/pr-subscribers-mlir-core
Author: Matthias Springer (matthias-springer)
Changes
The 1:N type converter derived from the 1:1 type converter and extends it with
1:N target materializations. This commit merges the two type converters and
stores 1:N target materialization
https://github.com/matthias-springer created
https://github.com/llvm/llvm-project/pull/113032
The 1:N type converter derived from the 1:1 type converter and extends it with
1:N target materializations. This commit merges the two type converters and
stores 1:N target materializations in the 1:1
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