https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/107548
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https://github.com/topperc approved this pull request.
LGTM, but wait for another review.
https://github.com/llvm/llvm-project/pull/107548
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wangpc-pp wrote:
> > > > Can we break the enabling down into more manageable pieces? I think
> > > > `enableUnalignedScalarMem() && (Subtarget->hasStdExtZbb() ||
> > > > Subtarget->hasStdExtZbkb() || IsZeroCmp)` might be a good starting
> > > > point.
> > >
> > >
> > > I'd be fine with this
https://github.com/wangpc-pp edited
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@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/115090
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/112842
>From a5e5b2c05c6026e855f1534b040c353ee638c178 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 18 Oct 2024 09:40:34 +0400
Subject: [PATCH] clang/HIP: Remove requires system-linux from some driver
tests
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113019
>From 63a199325b085599e1d66c241c7a9beca667dfb3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:18:45 +0400
Subject: [PATCH] AMDGPU: Mark grid size loads with range metadata
Only handles t
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/115060
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https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/115059
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https://github.com/llvm/llvm-project/pull/113019
>From 64d530b7c139da8aec7ede71fd201cb751a4072d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:18:45 +0400
Subject: [PATCH] AMDGPU: Mark grid size loads with range metadata
Only handles t
arsenm wrote:
### Merge activity
* **Nov 5, 3:43 PM EST**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/113751).
https://github.com/llvm/llvm-project/pull/113751
__
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/115059
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Only select to a VGPR if it's trivally used in VGPR only contexts.
This fixes mishandling frame indexes used in SGPR only contexts,
like inline assembly constraints.
This is suboptimal in the common
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Further extend workaround for the lack of proper regbankselect
for frame indexes.
---
Full diff: https://github.com/llvm/llvm-project/pull/115059.diff
2 Files Affected:
- (modified) llvm/lib/Targ
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/115059?utm_source=stack-comment-downstack-mergeability-warning";
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/115060?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/115059
Further extend workaround for the lack of proper regbankselect
for frame indexes.
>From 493a45c9a65aca2402c950bae122bad477e0e5b0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 1 Nov 2024 12:24:37 -0700
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/114010
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arichardson wrote:
> I think this change would benefit from an RFC on discourse, for wider
> visibility.
>
> Something that's not super clear to me is how to reconcile the statements
> about pointer/integer casts and in-memory type punning. I'd expect that
> ptrtoint returns an i128 value and
topperc wrote:
> > > Can we break the enabling down into more manageable pieces? I think
> > > `enableUnalignedScalarMem() && (Subtarget->hasStdExtZbb() ||
> > > Subtarget->hasStdExtZbkb() || IsZeroCmp)` might be a good starting point.
> >
> >
> > I'd be fine with this type of approach.
>
>
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/114311
>From e518d75b613f843747bc39ba35c95076caa37c75 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 29 Oct 2024 15:30:51 -0700
Subject: [PATCH] ValueTracking: Allow getUnderlyingObject to look at vectors
We
https://github.com/smithp35 edited
https://github.com/llvm/llvm-project/pull/113817
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https://github.com/smithp35 commented:
A few small suggestions from me.
https://github.com/llvm/llvm-project/pull/113817
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@@ -92,6 +92,10 @@ enum RelExpr {
R_AARCH64_PAGE_PC,
R_AARCH64_RELAX_TLS_GD_TO_IE_PAGE_PC,
R_AARCH64_TLSDESC_PAGE,
+ R_AARCH64_AUTH_TLSDESC_PAGE,
+ // TODO: maybe it's better to rename this expression
+ // to avoid name conflict with dynamic reloc
+ R_AARCH64_AUTH_TLS
@@ -0,0 +1,134 @@
+// REQUIRES: aarch64
+// RUN: rm -rf %t && split-file %s %t && cd %t
+
+//--- a.s
+
+.section .tbss,"awT",@nobits
+.global a
+a:
+.xword 0
+
+//--- ok.s
+
+// RUN: llvm-mc -filetype=obj -triple=aarch64-pc-linux -mattr=+pauth ok.s -o
ok.o
+// RUN: ld.lld -shared
@@ -1352,6 +1352,36 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr
expr, RelType type,
return 1;
}
+ auto fatalBothAuthAndNonAuth = [&sym]() {
+fatal("both AUTH and non-AUTH TLSDESC entries for '" + sym.getName() +
smithp35 wrote:
Can
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/113751
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shiltian wrote:
bump
https://github.com/llvm/llvm-project/pull/114438
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vitalybuka wrote:
Uploaded by mistake.
https://github.com/llvm/llvm-project/pull/115030
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shiltian wrote:
bump
https://github.com/llvm/llvm-project/pull/114726
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Author: Vitaly Buka
Date: 2024-11-05T09:44:36-08:00
New Revision: a3efa16d8fd2efc5d1ed8bc984e58c908202b048
URL:
https://github.com/llvm/llvm-project/commit/a3efa16d8fd2efc5d1ed8bc984e58c908202b048
DIFF:
https://github.com/llvm/llvm-project/commit/a3efa16d8fd2efc5d1ed8bc984e58c908202b048.diff
L
https://github.com/vitalybuka created
https://github.com/llvm/llvm-project/pull/115031
This reverts commit dd6f380c8837c7df135a871250f8a10ee0abb101.
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https://github.com/llvm/llvm-project/pull/115028
This reverts commit 67edb0ebbd5bb1139dc0dac9bf1ba6f1aa56c7ce.
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Author: Vitaly Buka
Date: 2024-11-05T09:38:28-08:00
New Revision: 106d54be69070e26c1b68f3f62ff4fa6c53d23b9
URL:
https://github.com/llvm/llvm-project/commit/106d54be69070e26c1b68f3f62ff4fa6c53d23b9
DIFF:
https://github.com/llvm/llvm-project/commit/106d54be69070e26c1b68f3f62ff4fa6c53d23b9.diff
L
https://github.com/vitalybuka closed
https://github.com/llvm/llvm-project/pull/115031
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/113874
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vitalybuka wrote:
Uploaded by mistake.
https://github.com/llvm/llvm-project/pull/115028
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vitalybuka wrote:
Uploaded by mistake.
https://github.com/llvm/llvm-project/pull/115031
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llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
This reverts commit a9f829a3d7556593e0814080c8e33eca09e3a51e.
---
Patch is 25.32 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/115030.diff
1
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
This reverts commit 67edb0ebbd5bb1139dc0dac9bf1ba6f1aa56c7ce.
---
Patch is 23.28 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/115028.diff
1
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
This reverts commit dd6f380c8837c7df135a871250f8a10ee0abb101.
---
Patch is 25.32 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/115031.diff
1
https://github.com/vitalybuka created
https://github.com/llvm/llvm-project/pull/115030
This reverts commit a9f829a3d7556593e0814080c8e33eca09e3a51e.
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@@ -1,5 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o
/dev/null 2>&1 < %s | FileCheck %s
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \
--
Author: Felipe de Azevedo Piovezan
Date: 2024-11-05T08:43:16-08:00
New Revision: d560dcabad287952024ffb0014cfcce1f4672535
URL:
https://github.com/llvm/llvm-project/commit/d560dcabad287952024ffb0014cfcce1f4672535
DIFF:
https://github.com/llvm/llvm-project/commit/d560dcabad287952024ffb0014cfcce1f
petar-avramovic wrote:
Added LLVM_DEBUG around dumps, RB->RegBank rename for methods and class names
https://github.com/llvm/llvm-project/pull/112864
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@@ -217,6 +217,74 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr
&I) const {
return true;
}
+bool AMDGPUInstructionSelector::selectCOPY_SCC_VCC(MachineInstr &I) const {
petar-avramovic wrote:
This allows for more registers to be allocated to sg
@@ -697,6 +697,15 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
}
+MachineInstrBuilder
+MachineIRBuilder::buildUnmerge(MachineRegisterInfo::VRegAttrs Attrs,
+ const
@@ -69,11 +82,297 @@ FunctionPass *llvm::createAMDGPURegBankLegalizePass() {
return new AMDGPURegBankLegalize();
}
-using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ stat
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/113751
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113019
>From 8c4d57e8f1039101b380d13c69986870365a2d4e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:18:45 +0400
Subject: [PATCH] AMDGPU: Mark grid size loads with range metadata
Only handles t
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113018
>From 27426a189d748ea66ad4c16f3fbee445ad1643e5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 18 Oct 2024 23:05:51 +0400
Subject: [PATCH 1/4] AMDGPU: Propagate amdgpu-max-num-workgroups attribute
I'm n
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113038
>From 6981d5ad80130130d373b8c879a88b7d727b0115 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:39:06 +0400
Subject: [PATCH] clang/AMDGPU: Emit grid size builtins with range metadata
These
@@ -66,9 +81,232 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From a8d15f3f4854a364fc0b905544840112283b41a3 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 74a1970b576cb6943271614cfe616459cd73956c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/statham-arm approved this pull request.
Sounds like a good idea to me!
https://github.com/llvm/llvm-project/pull/115006
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vhscampos wrote:
FYI I added a test for `-print-multi-lib` and its interaction with
`ExtraBuildArgs`.
https://github.com/llvm/llvm-project/pull/110659
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https://github.com/vhscampos updated
https://github.com/llvm/llvm-project/pull/110659
>From f2525efdd1f70c59923220b787be005903bdced5 Mon Sep 17 00:00:00 2001
From: Victor Campos
Date: Thu, 26 Sep 2024 14:44:33 +0100
Subject: [PATCH 1/3] [Multilib] Custom flags processing for library selection
github-actions[bot] wrote:
⚠️ We detected that you are using a GitHub private e-mail address to contribute
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llvmbot wrote:
@statham-arm What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/115006
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/115006
Backport 8aa9d6206ce55bdaaf422839c351fbd63f033b89
Requested by: @XrXr
>From aebbc1f67998ef1646f023ced799d921098ab6bc Mon Sep 17 00:00:00 2001
From: Alan Wu
Date: Fri, 16 Aug 2024 08:16:17 -0400
Subject: [PATCH
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Victor Campos (vhscampos)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/114998.diff
1 Files Affected:
- (modified) clang/docs/Multilib.rst (+116)
``diff
diff --git a/clang/docs/Multilib.rst b/clang/docs/Mu
https://github.com/vhscampos created
https://github.com/llvm/llvm-project/pull/114998
None
>From 02161c1c4754b15450ae81538c22b77501a809ca Mon Sep 17 00:00:00 2001
From: Victor Campos
Date: Tue, 5 Nov 2024 14:22:06 +
Subject: [PATCH] Add documentation for Multilib custom flags
---
clang/d
https://github.com/erichkeane approved this pull request.
https://github.com/llvm/llvm-project/pull/114951
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
Author: Walter Erquinigo
Date: 2024-11-05T07:11:32-05:00
New Revision: 84633d7ccc926abff46c6480dbe7ccc7e48247ce
URL:
https://github.com/llvm/llvm-project/commit/84633d7ccc926abff46c6480dbe7ccc7e48247ce
DIFF:
https://github.com/llvm/llvm-project/commit/84633d7ccc926abff46c6480dbe7ccc7e48247ce.di
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
Changes
We can convert non-power-of-2 types into extended value types
and then they will be widen.
---
Patch is 253.31 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-pro
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/114971
We can convert non-power-of-2 types into extended value types
and then they will be widen.
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https://github.com/optimisan closed
https://github.com/llvm/llvm-project/pull/114746
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optimisan wrote:
The default value is false, but two targets are setting it to true.
Currently MachineSink is added by generic TargetPassConfig. Can add the option
to `CGPassBuilderOptions` so targets can set it there instead.
https://github.com/llvm/llvm-project/pull/114746
__
@@ -15440,9 +15440,25 @@ bool BoUpSLP::collectValuesToDemote(
MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)));
});
};
+auto AbsChecker = [&](unsigned BitWidth, unsigned OrigBitWidth) {
+ assert(BitWidth <= OrigBitWidth && "Unexp
@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -15440,9 +15440,25 @@ bool BoUpSLP::collectValuesToDemote(
MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)));
});
};
+auto AbsChecker = [&](unsigned BitWidth, unsigned OrigBitWidth) {
+ assert(BitWidth <= OrigBitWidth && "Unexp
https://github.com/DavidSpickett commented:
LGTM but a LoongArch expert should give the final approval.
https://github.com/llvm/llvm-project/pull/114742
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https://github.com/wangleiat updated
https://github.com/llvm/llvm-project/pull/114742
>From f390561ee9c49dd10f0b13b79b713624664d7da2 Mon Sep 17 00:00:00 2001
From: wanglei
Date: Mon, 4 Nov 2024 17:12:03 +0800
Subject: [PATCH 1/2] comply with code style
Created using spr 1.3.5-bogner
---
lldb/
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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