@@ -1,5 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o
/dev/null 2>&1 < %s | FileCheck %s
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \
--
https://github.com/SixWeining approved this pull request.
LGTM. But should land after #114741.
https://github.com/llvm/llvm-project/pull/114742
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@@ -447,12 +561,12 @@ createFlowFunction(const
BinaryFunction::BasicBlockOrderType &BlockOrder) {
/// of the basic blocks in the binary, the count is "matched" to the block.
/// Similarly, if both the source and the target of a count in the profile are
/// matched to a jump in
@@ -482,11 +596,68 @@ matchWeightsByHashes(BinaryContext &BC,
<< Twine::utohexstr(BB->getHash()) << "\n");
}
StaleMatcher Matcher;
+ // Collects function pseudo probes for use in the StaleMatcher.
+ if (opts::StaleMatchingWithPseudoProbes) {
+con
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/115162
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wlei-llvm wrote:
> > Ping @wlei-llvm
>
> Sorry for the delay. The new version addressed my last comment (with just
> minor nits). However, I didn't fully follow the new features related to
> `ProbeMatchSpecs` stuffs. Could you add more descriptions to the diff
> summary? Or if it’s not a lot
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https://github.com/xen0n approved this pull request.
Test failures shouldn't be relevant.
https://github.com/llvm/llvm-project/pull/114958
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/115214
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/115090
>From f3d99e4ae92e407ebc2ef3f6b8e4017b397d34eb Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Nov 2024 12:28:07 -0800
Subject: [PATCH] [AMDGPU] Simplify dpp builtin handling
DPP intrinsics c
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113019
>From cc4a77290bc498c22cf5b848c39e4effc8103ba5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:18:45 +0400
Subject: [PATCH] AMDGPU: Mark grid size loads with range metadata
Only handles t
Author: Alexander Richardson
Date: 2024-11-06T15:06:15-08:00
New Revision: 5d95a55a43daea00d42d771892037bd3aa44e291
URL:
https://github.com/llvm/llvm-project/commit/5d95a55a43daea00d42d771892037bd3aa44e291
DIFF:
https://github.com/llvm/llvm-project/commit/5d95a55a43daea00d42d771892037bd3aa44e29
@@ -466,6 +470,7 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const
Triple &T,
case GK_GFX942:
case GK_GFX941:
case GK_GFX940:
+case GK_GFX9_4_GENERIC:
shiltian wrote:
This needs to be updated as well
https://github.com/llvm/llvm-proje
@@ -775,6 +775,11 @@ let SubtargetPredicate = HasFP8Insts, is_gfx940_xdl = 1 in
{
defm V_MFMA_F32_32X32X16_FP8_FP8 : MAIInst<"v_mfma_f32_32x32x16_fp8_fp8",
"F32_I64_X16",int_amdgcn_mfma_f32_32x32x16_fp8_fp8>;
} // End SubtargetPredicate = HasFP8Insts, is_gfx940_xdl = 1
https://github.com/shiltian deleted
https://github.com/llvm/llvm-project/pull/115190
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Shilei Tian (shiltian)
Changes
The feature itself is not new. Just to use it to guard corresponding
instructions.
---
Full diff: https://github.com/llvm/llvm-project/pull/115214.diff
3 Files Affected:
- (modified) llvm/lib/Targ
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/115214?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/115214
The feature itself is not new. Just to use it to guard corresponding
instructions.
>From 4077a199a263252ef45895e2c9b4e6375988fa88 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 6 Nov 2024 16:15:50 -0500
rampitec wrote:
> Should also teach instcombine to fold bitcast + app
It still needs downstack change to handle i8:
https://github.com/llvm/llvm-project/pull/114887
https://github.com/llvm/llvm-project/pull/115090
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Author: Justin Fargnoli
Date: 2024-11-06T12:10:29-08:00
New Revision: 71a162cbf76febd1bc87a0ab6292ed3c89f947bc
URL:
https://github.com/llvm/llvm-project/commit/71a162cbf76febd1bc87a0ab6292ed3c89f947bc
DIFF:
https://github.com/llvm/llvm-project/commit/71a162cbf76febd1bc87a0ab6292ed3c89f947bc.dif
https://github.com/arichardson updated
https://github.com/llvm/llvm-project/pull/115085
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https://github.com/llvm/llvm-project/pull/115085
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/115090
>From 7ccac58706b2d7e54c8498818b560af490a70eac Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Nov 2024 12:28:07 -0800
Subject: [PATCH] [AMDGPU] Simplify dpp builtin handling
DPP intrinsics c
https://github.com/arsenm approved this pull request.
Should also teach instcombine to fold bitcast + app
https://github.com/llvm/llvm-project/pull/115090
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@@ -171,145 +76,88 @@ set(sources
unit-map.cpp
unit.cpp
utf.cpp
- ${FORTRAN_MODULE_OBJECTS}
)
-include(AddFlangOffloadRuntime)
-
-# List of files that are buildable for all devices.
-set(supported_files
- ISO_Fortran_binding.cpp
- allocatable.cpp
- allocator-regist
https://github.com/clementval edited
https://github.com/llvm/llvm-project/pull/110217
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@@ -171,145 +76,88 @@ set(sources
unit-map.cpp
unit.cpp
utf.cpp
- ${FORTRAN_MODULE_OBJECTS}
)
-include(AddFlangOffloadRuntime)
-
-# List of files that are buildable for all devices.
-set(supported_files
- ISO_Fortran_binding.cpp
- allocatable.cpp
- allocator-regist
@@ -171,145 +76,88 @@ set(sources
unit-map.cpp
unit.cpp
utf.cpp
- ${FORTRAN_MODULE_OBJECTS}
)
-include(AddFlangOffloadRuntime)
-
-# List of files that are buildable for all devices.
-set(supported_files
- ISO_Fortran_binding.cpp
- allocatable.cpp
- allocator-regist
@@ -171,145 +76,88 @@ set(sources
unit-map.cpp
unit.cpp
utf.cpp
- ${FORTRAN_MODULE_OBJECTS}
)
-include(AddFlangOffloadRuntime)
-
-# List of files that are buildable for all devices.
-set(supported_files
- ISO_Fortran_binding.cpp
- allocatable.cpp
- allocator-regist
https://github.com/ldionne approved this pull request.
LGTM, thanks for the cleanup!
https://github.com/llvm/llvm-project/pull/115086
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@@ -171,145 +76,88 @@ set(sources
unit-map.cpp
unit.cpp
utf.cpp
- ${FORTRAN_MODULE_OBJECTS}
)
-include(AddFlangOffloadRuntime)
-
-# List of files that are buildable for all devices.
-set(supported_files
- ISO_Fortran_binding.cpp
- allocatable.cpp
- allocator-regist
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Anatoly Trosinenko (atrosinenko)
Changes
As function calls do not generally preserve X16 and X17, it is beneficial
to allow AddrDisc operand of B(L)RA instruction to reside in these
registers and make use of this condition when co
https://github.com/atrosinenko ready_for_review
https://github.com/llvm/llvm-project/pull/115185
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atrosinenko wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/115185?utm_source=stack-comment-downstack-mergeability-warni
https://github.com/atrosinenko created
https://github.com/llvm/llvm-project/pull/115185
As function calls do not generally preserve X16 and X17, it is beneficial
to allow AddrDisc operand of B(L)RA instruction to reside in these
registers and make use of this condition when computing the discrim
https://github.com/ldionne commented:
I think the most effective way of settling on the bit-stealing issue would be
to benchmark something like this:
1. Set up ~100 functions that do random stuff (e.g. they all return numbers
from 1 to 100)
2. Set up a `std::vector>` with some large
number of
https://github.com/DavidTruby edited
https://github.com/llvm/llvm-project/pull/112188
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https://github.com/DavidTruby approved this pull request.
LGTM, but someone else should probably approve as this is quite a large change.
I don't think this one is an NFC because of the changes mentioned above by
@jeanPerier
https://github.com/llvm/llvm-project/pull/112188
arichardson wrote:
> Can't we do the same for libc++ as well?
Looks like CI is happy on this one so I'll try the same with libc++ next.
https://github.com/llvm/llvm-project/pull/115086
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@@ -0,0 +1,165 @@
+#===-- CMakeLists.txt
--===#
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-
https://github.com/jhuber6 edited
https://github.com/llvm/llvm-project/pull/110217
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@@ -270,13 +271,15 @@ function(runtime_default_target)
-DLLVM_BUILD_TOOLS=${LLVM_BUILD_TOOLS}
-DCMAKE_C_COMPILER_WORKS=ON
-DCMAKE_CXX_COMPILER_WORKS=ON
+
@@ -0,0 +1,165 @@
+#===-- CMakeLists.txt
--===#
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-
@@ -221,6 +230,9 @@ function(llvm_ExternalProject_Add name source_dir)
-DCMAKE_ASM_COMPILER=${LLVM_RUNTIME_OUTPUT_INTDIR}/clang${CMAKE_EXECUTABLE_SUFFIX})
endif()
endif()
+if(FLANG_IN_TOOLCHAIN)
+ list(APPEND compiler_args
-DCMAKE_
@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind
optsize {
;
; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a
https://github.com/lukel97 approved this pull request.
Good catch. I double checked and we're setting ElementsDependOnVL and
ElementsDependOnMask for VCPOP_M and VFIRST_M so adding RISCVMaskedPseudo
should be safe.
https://github.com/llvm/llvm-project/pull/115162
__
@@ -1150,6 +1150,7 @@ class VPseudoUnaryNoMaskGPROut :
class VPseudoUnaryMaskGPROut :
Pseudo<(outs GPR:$rd),
(ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
+ RISCVMaskedPseudo,
lukel97 wrote:
Nit, add instead of adding it in the cl
https://github.com/lukel97 edited
https://github.com/llvm/llvm-project/pull/115162
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https://github.com/Meinersbur edited
https://github.com/llvm/llvm-project/pull/110298
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@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind
optsize {
;
; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a
@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind
optsize {
;
; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
Changes
We seem to forget these two instructions.
---
Full diff: https://github.com/llvm/llvm-project/pull/115162.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+12-
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/115162
We seem to forget these two instructions.
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https://github.com/ldionne commented:
Can't we do the same for libc++ as well?
https://github.com/llvm/llvm-project/pull/115086
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https://github.com/wangleiat updated
https://github.com/llvm/llvm-project/pull/114742
>From f390561ee9c49dd10f0b13b79b713624664d7da2 Mon Sep 17 00:00:00 2001
From: wanglei
Date: Mon, 4 Nov 2024 17:12:03 +0800
Subject: [PATCH 1/3] comply with code style
Created using spr 1.3.5-bogner
---
lldb/
@@ -2525,5 +2527,21 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
Options.LoadSizes = {8, 4, 2, 1};
else
Options.LoadSizes = {4, 2, 1};
+ if (IsZeroCmp && ST->hasVInstructions()) {
wangpc-pp wrote:
Good catch! I will
ilya-biryukov wrote:
> > > Sorry, could you provide the hash id for the commit that avoid the
> > > warning?
> >
> >
> > I tried running this on head and unfortunately it reproduces on head as
> > well :( So this looks like a sleeper issue which now also gets triggered by
> > this PR in a no
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/115090
>From 084e347f5fb6e9068313ad4dbc53b44c2d4cee69 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Nov 2024 12:28:07 -0800
Subject: [PATCH] [AMDGPU] Simplify dpp builtin handling
DPP intrinsics c
@@ -14520,17 +14520,78 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType
IndexType, SelectionDAG &D
return true;
}
+/// Try to map an integer comparison with size > XLEN to vector instructions
+/// before type legalization splits it up into chunks.
+static SDValue
+c
https://github.com/lukel97 edited
https://github.com/llvm/llvm-project/pull/114517
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@@ -2525,5 +2527,21 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
Options.LoadSizes = {8, 4, 2, 1};
else
Options.LoadSizes = {4, 2, 1};
+ if (IsZeroCmp && ST->hasVInstructions()) {
lukel97 wrote:
Doesn't this mean tha
@@ -14520,17 +14520,78 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType
IndexType, SelectionDAG &D
return true;
}
+/// Try to map an integer comparison with size > XLEN to vector instructions
+/// before type legalization splits it up into chunks.
+static SDValue
+c
Author: Dominik Adamski
Date: 2024-11-06T09:22:17+01:00
New Revision: 74419f801de610cf20a78af5d9562e1eb2387c23
URL:
https://github.com/llvm/llvm-project/commit/74419f801de610cf20a78af5d9562e1eb2387c23
DIFF:
https://github.com/llvm/llvm-project/commit/74419f801de610cf20a78af5d9562e1eb2387c23.dif
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
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