[llvm-branch-commits] [llvm] AMDGPU: Handle demanded subvectors for readfirstlane (PR #128648)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/128648 >From ce66b73ac989b8f4d8ec03f704f2e72ee30a3b42 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 25 Feb 2025 12:51:44 +0700 Subject: [PATCH] AMDGPU: Handle demanded subvectors for readfirstlane --- .../A

[llvm-branch-commits] [clang] [MC/DC] Enable nested expressions (PR #125413)

@@ -275,49 +276,57 @@ struct MapRegionCounters : public RecursiveASTVisitor { // an AST Stmt node. MC/DC will use it to to signal when the top of a // logical operation (boolean expression) nest is encountered. bool dataTraverseStmtPost(Stmt *S) { -/// If MC/DC is n

[llvm-branch-commits] [llvm] AMDGPU: Simplify demanded vector elts of readfirstlane sources (PR #128646)

arsenm wrote: ### Merge activity * **Feb 28, 12:52 AM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/128646). https://github.com/llvm/llvm-project/pull/128646

[llvm-branch-commits] [clang] [MC/DC] Enable nested expressions (PR #125413)

@@ -275,49 +276,57 @@ struct MapRegionCounters : public RecursiveASTVisitor { // an AST Stmt node. MC/DC will use it to to signal when the top of a // logical operation (boolean expression) nest is encountered. bool dataTraverseStmtPost(Stmt *S) { -/// If MC/DC is n

[llvm-branch-commits] [clang] [MC/DC] Enable nested expressions (PR #125413)

@@ -228,45 +228,46 @@ struct MapRegionCounters : public RecursiveASTVisitor { /// The stacks are also used to find error cases and notify the user. A /// standard logical operator nest for a boolean expression could be in a form /// similar to this: "x = a && b && c &&

[llvm-branch-commits] [llvm] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (PR #129059)

https://github.com/rampitec approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/129059 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)

https://github.com/fmayer updated https://github.com/llvm/llvm-project/pull/128977 >From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Wed, 26 Feb 2025 17:12:43 -0800 Subject: [PATCH 1/3] fmt Created using spr 1.3.4 --- clang/lib/CodeGen/CGExpr.cp

[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)

https://github.com/fmayer updated https://github.com/llvm/llvm-project/pull/128977 >From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Wed, 26 Feb 2025 17:12:43 -0800 Subject: [PATCH 1/3] fmt Created using spr 1.3.4 --- clang/lib/CodeGen/CGExpr.cp

[llvm-branch-commits] [clang] [HLSL] Implement explicit layout for default constant buffer ($Globals) (PR #128991)

@@ -179,21 +179,45 @@ createBufferHandleType(const HLSLBufferDecl *BufDecl) { return cast(QT.getTypePtr()); } +// Iterates over all declarations in the HLSL buffer and based on the +// packoffset or register(c#) annotations it fills outs the Layout +// vector with the user-s

[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)

https://github.com/fmayer updated https://github.com/llvm/llvm-project/pull/128977 >From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Wed, 26 Feb 2025 17:12:43 -0800 Subject: [PATCH 1/3] fmt Created using spr 1.3.4 --- clang/lib/CodeGen/CGExpr.cp

[llvm-branch-commits] [clang] [HLSL] Implement explicit layout for default constant buffer ($Globals) (PR #128991)

@@ -179,21 +179,45 @@ createBufferHandleType(const HLSLBufferDecl *BufDecl) { return cast(QT.getTypePtr()); } +// Iterates over all declarations in the HLSL buffer and based on the +// packoffset or register(c#) annotations it fills outs the Layout +// vector with the user-s

[llvm-branch-commits] [clang] [HLSL] Implement explicit layout for default constant buffer ($Globals) (PR #128991)

https://github.com/hekota updated https://github.com/llvm/llvm-project/pull/128991 >From e982a61657da5eb4c7f2618c95f0c6d3493cb854 Mon Sep 17 00:00:00 2001 From: Helena Kotas Date: Wed, 26 Feb 2025 19:14:20 -0800 Subject: [PATCH 1/3] [HLSL] Implement explicit layout for default constant buffer

[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)

https://github.com/fmayer updated https://github.com/llvm/llvm-project/pull/128977 >From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Wed, 26 Feb 2025 17:12:43 -0800 Subject: [PATCH 1/3] fmt Created using spr 1.3.4 --- clang/lib/CodeGen/CGExpr.cp

[llvm-branch-commits] [llvm] [AArch64] Fall back to SDAG for instructions with emulated TLS variables (PR #129076)

sschaller wrote: Will do, sorry about that. https://github.com/llvm/llvm-project/pull/129076 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Fall back to SDAG for instructions with emulated TLS variables (PR #129076)

https://github.com/nikic closed https://github.com/llvm/llvm-project/pull/129076 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Fall back to SDAG for instructions with emulated TLS variables (PR #129076)

https://github.com/sschaller edited https://github.com/llvm/llvm-project/pull/129076 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Fall back to SDAG for instructions with emulated TLS variables (PR #129076)

nikic wrote: This needs to go into the main branch first, before it can be consider for backport (to LLVM 20 only). I'll close this PR due to the mass-subscribe. https://github.com/llvm/llvm-project/pull/129076 ___ llvm-branch-commits mailing list ll

[llvm-branch-commits] [BOLT] Fix merge-fdata for memory events (PR #128108)

https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/128108 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [BOLT] Fix merge-fdata for memory events (PR #128108)

https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/128108 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/129058 >From 6898b936d27a6cc5dd8c0c4c8b45f8b359188f5b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Feb 2025 22:59:31 +0700 Subject: [PATCH 1/2] AMDGPU: Add mir test for agpr constant reg_sequence handlin

[llvm-branch-commits] [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/129058 >From 6898b936d27a6cc5dd8c0c4c8b45f8b359188f5b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Feb 2025 22:59:31 +0700 Subject: [PATCH 1/2] AMDGPU: Add mir test for agpr constant reg_sequence handlin

[llvm-branch-commits] [llvm] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (PR #129059)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/129059 >From b221f64e931ffd8ae0a6b288d8c192f80f851876 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 27 Feb 2025 20:40:52 +0700 Subject: [PATCH] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg cop

[llvm-branch-commits] [llvm] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (PR #129059)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/129059 >From b221f64e931ffd8ae0a6b288d8c192f80f851876 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 27 Feb 2025 20:40:52 +0700 Subject: [PATCH] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg cop

[llvm-branch-commits] [llvm] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (PR #129059)

https://github.com/Pierre-vh approved this pull request. https://github.com/llvm/llvm-project/pull/129059 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (PR #129059)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes This was trying to hack around the intermediate VGPR requirement to copy to AGPRs on gfx908. We should still use a copy for all reg-to-reg cases. This should matter less these days, as we reserve a V

[llvm-branch-commits] [llvm] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (PR #129059)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/129059 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes --- Patch is 28.27 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/129058.diff 1 Files Affected: - (added) llvm/test/CodeGen/AMDGPU/si-fold-operands-

[llvm-branch-commits] [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/129058 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (PR #129059)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/129059?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/129058?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/129058 None >From 3fe0c486507705493e24b75b480469bda885b086 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Feb 2025 22:59:31 +0700 Subject: [PATCH] AMDGPU: Add mir test for agpr constant reg_sequence handli

[llvm-branch-commits] [llvm] AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (PR #129059)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/129059 This was trying to hack around the intermediate VGPR requirement to copy to AGPRs on gfx908. We should still use a copy for all reg-to-reg cases. This should matter less these days, as we reserve a VGPR to handle

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Support -regalloc-npm options (PR #129035)

@@ -2,11 +2,17 @@ # RUN: llc -mtriple=amdgcn --passes='regallocfast,regallocfast,regallocfast' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=PASS # RUN: not llc -mtriple=amdgcn --passes='regallocfast' --print-pipeline-passes --filetype=null %s 2>&1

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Support -regalloc-npm options (PR #129035)

@@ -2,11 +2,17 @@ # RUN: llc -mtriple=amdgcn --passes='regallocfast,regallocfast,regallocfast' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=PASS # RUN: not llc -mtriple=amdgcn --passes='regallocfast' --print-pipeline-passes --filetype=null %s 2>&1

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Support -regalloc-npm options (PR #129035)

https://github.com/cdevadas commented: LGTM. https://github.com/llvm/llvm-project/pull/129035 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Support -regalloc-npm options (PR #129035)

@@ -2,11 +2,17 @@ # RUN: llc -mtriple=amdgcn --passes='regallocfast,regallocfast,regallocfast' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=PASS # RUN: not llc -mtriple=amdgcn --passes='regallocfast' --print-pipeline-passes --filetype=null %s 2>&1

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Support -regalloc-npm options (PR #129035)

https://github.com/cdevadas edited https://github.com/llvm/llvm-project/pull/129035 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: Reland "[LV]: Teach LV to recursively (de)interleave." (#125094) (PR #128389)

nikic wrote: I think this is something that @fhahn as the LoopVectorize maintainer should decide. I personally still don't see why this backport is necessary. https://github.com/llvm/llvm-project/pull/128389 ___ llvm-branch-commits mailing list llvm-b

[llvm-branch-commits] [clang] [clang-format] Fix a bug that changes keyword `or` to an identifier (PR #128996)

https://github.com/owenca milestoned https://github.com/llvm/llvm-project/pull/128996 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits