https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/130037
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https://github.com/NimishMishra approved this pull request.
Thanks. LGTM.
https://github.com/llvm/llvm-project/pull/130290
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llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: Helena Kotas (hekota)
Changes
Fixes #114126
---
Full diff: https://github.com/llvm/llvm-project/pull/130338.diff
5 Files Affected:
- (modified) clang/lib/CodeGen/CGDeclCXX.cpp (-3)
- (modified) clang/lib/CodeGen/CGHLSLRuntime.c
Author: Vitaly Buka
Date: 2025-03-07T17:45:57-08:00
New Revision: a7c76aa6112e36a74d91dcd8b08cb114a6727556
URL:
https://github.com/llvm/llvm-project/commit/a7c76aa6112e36a74d91dcd8b08cb114a6727556
DIFF:
https://github.com/llvm/llvm-project/commit/a7c76aa6112e36a74d91dcd8b08cb114a6727556.diff
L
llvmbot wrote:
@david-arm What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/129997
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https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/129473
>From e2dd98690a0f43b35ee22d59efeb04d2c7fead68 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Mon, 3 Mar 2025 12:26:08 +0900
Subject: [PATCH] detailed
---
llvm/include/llvm/ObjectYAML/CovMap.h | 9
@@ -0,0 +1,31 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -o - %s |
FileCheck %s
+
+// CHECK: !dx.rootsignatures = !{![[#FIRST_ENTRY:]], ![[#SECOND_ENTRY:]]}
+
+// CHECK: ![[#FIRST_ENTRY]] = !{ptr @FirstEntry, ![[#EMPTY:]]}
+// CHECK: ![[#EMPTY]] = !{
@@ -0,0 +1,108 @@
+//===- HLSLRootSignature.cpp - HLSL Root Signature helper objects
+//--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,31 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -o - %s |
FileCheck %s
+
+// CHECK: !dx.rootsignatures = !{![[#FIRST_ENTRY:]], ![[#SECOND_ENTRY:]]}
+
+// CHECK: ![[#FIRST_ENTRY]] = !{ptr @FirstEntry, ![[#EMPTY:]]}
+// CHECK: ![[#EMPTY]] = !{
@@ -0,0 +1,108 @@
+//===- HLSLRootSignature.cpp - HLSL Root Signature helper objects
+//--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,31 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -o - %s |
FileCheck %s
+
+// CHECK: !dx.rootsignatures = !{![[#FIRST_ENTRY:]], ![[#SECOND_ENTRY:]]}
+
+// CHECK: ![[#FIRST_ENTRY]] = !{ptr @FirstEntry, ![[#EMPTY:]]}
+// CHECK: ![[#EMPTY]] = !{
@@ -14,10 +14,16 @@
#ifndef LLVM_FRONTEND_HLSL_HLSLROOTSIGNATURE_H
#define LLVM_FRONTEND_HLSL_HLSLROOTSIGNATURE_H
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLForwardCompat.h"
joaosaffran wrote:
nit: are those needed?
https://github.com/llvm/llvm-p
optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130068?utm_source=stack-comment-downstack-mergeability-warning
rovka wrote:
> Is there any test for the revert scheduling portion of the change?
Sadly, no. It's a bit difficult to add.
https://github.com/llvm/llvm-project/pull/130047
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@@ -511,6 +511,14 @@ SIRegisterInfo::getLargestLegalSuperClass(const
TargetRegisterClass *RC,
Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const SIFrameLowering *TFI = ST.getFrameLowering();
const SIMachineFunctionInfo *FuncInfo = MF.getInfo
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/130338
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https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130055
>From 3e20edfc6f3b1bfa60f5d778ce98c1fb984b1aee Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 24 Sep 2024 09:57:25 +0200
Subject: [PATCH 1/7] [AMDGPU] Allocate scratch space for dVGPRs for CWSR
The CWSR tr
https://github.com/bob80905 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/130338
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@@ -125,15 +125,6 @@ class CGHLSLRuntime {
// End of reserved area for HLSL intrinsic getters.
//===--===//
- struct BufferResBinding {
hekota wrote:
The register number and space are u
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/130338
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@@ -11,59 +11,9 @@
//===--===//
#include "llvm/Frontend/HLSL/HLSLResource.h"
-#include "llvm/IR/IRBuilder.h"
-#include "llvm/IR/Metadata.h"
using namespace llvm;
using namespace llvm::hlsl;
-GlobalVaria
@@ -386,6 +386,16 @@ MCSection *TargetLoweringObjectFile::getSectionForConstant(
return DataSection;
}
+MCSection *TargetLoweringObjectFile::getSectionForConstant(
+const DataLayout &DL, SectionKind Kind, const Constant *C, Align
&Alignment,
+StringRef SectionPrefix
hekota wrote:
Reopening. I've accidentally deleted the pr branch this depends on and it
closed this PR.
https://github.com/llvm/llvm-project/pull/128991
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pawosm-arm wrote:
I can't merge it myself, it says `Cannot update this protected ref.`
https://github.com/llvm/llvm-project/pull/129566
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https://github.com/bob80905 commented:
LGTM. I'll leave the approval to someone with more expertise.
https://github.com/llvm/llvm-project/pull/130323
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@@ -11,59 +11,9 @@
//===--===//
#include "llvm/Frontend/HLSL/HLSLResource.h"
-#include "llvm/IR/IRBuilder.h"
-#include "llvm/IR/Metadata.h"
using namespace llvm;
using namespace llvm::hlsl;
-GlobalVaria
@@ -125,15 +125,6 @@ class CGHLSLRuntime {
// End of reserved area for HLSL intrinsic getters.
//===--===//
- struct BufferResBinding {
bob80905 wrote:
May I ask how the buffer register
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Helena Kotas (hekota)
Changes
`DXILResourceMDAnalysis` gathers information about resources from obsolete
resource metadata annotations that are going to be removed in a follow-up PR.
Part 1/2 of #114126
---
Patch is 33.16 KiB,
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Helena Kotas (hekota)
Changes
Fixes #114126
---
Full diff: https://github.com/llvm/llvm-project/pull/130338.diff
5 Files Affected:
- (modified) clang/lib/CodeGen/CGDeclCXX.cpp (-3)
- (modified) clang/lib/CodeGen/CGHLSLRuntime.cpp (-129
llvmbot wrote:
@llvm/pr-subscribers-hlsl
Author: Helena Kotas (hekota)
Changes
Fixes #114126
---
Full diff: https://github.com/llvm/llvm-project/pull/130338.diff
5 Files Affected:
- (modified) clang/lib/CodeGen/CGDeclCXX.cpp (-3)
- (modified) clang/lib/CodeGen/CGHLSLRuntime.cpp (-129)
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/130323
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https://github.com/hekota created
https://github.com/llvm/llvm-project/pull/130338
Fixes #114126
>From c574bedb001f61f4bcdbf00613eec932028cf392 Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Fri, 7 Mar 2025 12:09:33 -0800
Subject: [PATCH] [HLSL] Remove old resource annotations
Fixes #11412
@@ -228,6 +229,66 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
return false;
}
+bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
+ MachineRegisterInfo::VRegAttrs BoolS1 = {ST->getBoolRC(), LLT::scalar(1)};
+ initializeLaneMaskRegisterAttributes
https://github.com/hekota reopened
https://github.com/llvm/llvm-project/pull/128991
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@@ -228,6 +229,66 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
return false;
}
+bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
+ MachineRegisterInfo::VRegAttrs BoolS1 = {ST->getBoolRC(), LLT::scalar(1)};
+ initializeLaneMaskRegisterAttributes
https://github.com/nhaehnle commented:
Thanks, this now looks good to me in terms of the overall flow. I have a bunch
of nitpickier, mostly style-related comments.
https://github.com/llvm/llvm-project/pull/124299
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https://github.com/hekota closed
https://github.com/llvm/llvm-project/pull/128991
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https://github.com/hekota created
https://github.com/llvm/llvm-project/pull/130323
`DXILResourceMDAnalysis` gathers information about resources from obsolete
resource metadata annotations that are going to be removed in a follow-up PR.
Part 1/2 of #114126
>From 80765757f067527816c4c8b9d728169
@@ -228,6 +229,66 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
return false;
}
+bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
+ MachineRegisterInfo::VRegAttrs BoolS1 = {ST->getBoolRC(), LLT::scalar(1)};
+ initializeLaneMaskRegisterAttributes
@@ -228,6 +229,66 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
return false;
}
+bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
+ MachineRegisterInfo::VRegAttrs BoolS1 = {ST->getBoolRC(), LLT::scalar(1)};
+ initializeLaneMaskRegisterAttributes
https://github.com/nhaehnle edited
https://github.com/llvm/llvm-project/pull/124299
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@@ -228,6 +229,66 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
return false;
}
+bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
+ MachineRegisterInfo::VRegAttrs BoolS1 = {ST->getBoolRC(), LLT::scalar(1)};
+ initializeLaneMaskRegisterAttributes
https://github.com/tblah approved this pull request.
Thank you for the quick fix. This does fix the issue I saw.
https://github.com/llvm/llvm-project/pull/130290
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https://github.com/nhaehnle approved this pull request.
Thanks!
https://github.com/llvm/llvm-project/pull/124298
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https://github.com/nhaehnle approved this pull request.
https://github.com/llvm/llvm-project/pull/128702
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https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/130146
>From 98df18461bb06afa06b8968b157a3c5a5cf50324 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 6 Mar 2025 08:51:34 -0600
Subject: [PATCH 1/4] [flang][OpenMP] Parse cancel-directive-name as clause
nunoplopes wrote:
FWIW, we have been using this patch internally and it helps substancial in a
couple of benchmarks.
https://github.com/llvm/llvm-project/pull/129776
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130067
>From b4d0fbae6828037b73903aef6a122458c8ce48fa Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:56:04 +
Subject: [PATCH] [CodeGen][NPM] Port BranchRelaxation to NPM
This completes the Pr
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/130146
>From 98df18461bb06afa06b8968b157a3c5a5cf50324 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 6 Mar 2025 08:51:34 -0600
Subject: [PATCH 1/3] [flang][OpenMP] Parse cancel-directive-name as clause
llvmbot wrote:
@llvm/pr-subscribers-flang-fir-hlfir
Author: None (jeanPerier)
Changes
Reland #114002 with an implementation of the FIXME that should solve
the regressions that have been seen.
The first commit is the original PR, the second is the fix.
---
Patch is 42.75 KiB, truncated t
@@ -112,21 +117,52 @@ bool
StaticDataSplitter::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
+const Constant *
+StaticDataSplitter::getConstant(const MachineOperand &Op,
+const TargetMachine &TM,
+
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: None (llvmbot)
Changes
Backport bae6644e1227b2555f92b1962dac6c2444eaaaf2
Requested by: @SixWeining
---
Full diff: https://github.com/llvm/llvm-project/pull/130009.diff
3 Files Affected:
- (modified) llvm/docs/LangRef.rst (+2)
- (mod
llvmbot wrote:
@llvm/pr-subscribers-llvm-selectiondag
Author: Diana Picus (rovka)
Changes
The llvm.amdgcn.cs.chain intrinsic has a 'flags' operand which may indicate
that we want to reallocate the VGPRs before performing the call.
A call with the following arguments:
```
llvm.amdgcn.cs.c
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/130146
>From 98df18461bb06afa06b8968b157a3c5a5cf50324 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 6 Mar 2025 08:51:34 -0600
Subject: [PATCH 1/2] [flang][OpenMP] Parse cancel-directive-name as clause
https://github.com/jeanPerier created
https://github.com/llvm/llvm-project/pull/130290
Reland #114002 with an implementation of the FIXME that should solve the
regressions that have been seen.
The first commit is the original PR, the second is the fix.
>From ad33569ce2ff3a97ea9767817e37ea85119
@@ -0,0 +1,263 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+dynamic-vgpr < %s
| FileCheck -check-prefix=CHECK %s
+
+; Make sure we use a stack pointer and allo
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130055
>From 3e20edfc6f3b1bfa60f5d778ce98c1fb984b1aee Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 24 Sep 2024 09:57:25 +0200
Subject: [PATCH 1/6] [AMDGPU] Allocate scratch space for dVGPRs for CWSR
The CWSR tr
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129865
>From 20188b3b5d1dbfea562b0912bf4624d9c7c18ca1 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 10:11:27 +
Subject: [PATCH] [CodeGen][NPM] Port XRayInstrumentation to NPM
---
.../llvm/Code
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/128520
>From e8245205377e9f81ac768c9193ea902037c24750 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 17 Nov 2023 14:21:52 +0900
Subject: [PATCH] AMDGPU: Implement bitcode autoupgrade for old style enqueue
blo
Author: Tom Eccles
Date: 2025-03-07T12:21:57Z
New Revision: 6e3e9f6b34d5f08c8b0b77e60fe1526db7e69633
URL:
https://github.com/llvm/llvm-project/commit/6e3e9f6b34d5f08c8b0b77e60fe1526db7e69633
DIFF:
https://github.com/llvm/llvm-project/commit/6e3e9f6b34d5f08c8b0b77e60fe1526db7e69633.diff
LOG: Re
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/128520
>From e8245205377e9f81ac768c9193ea902037c24750 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 17 Nov 2023 14:21:52 +0900
Subject: [PATCH] AMDGPU: Implement bitcode autoupgrade for old style enqueue
blo
Author: Jan Patrick Lehr
Date: 2025-03-07T13:13:26+01:00
New Revision: a25b6a1976cc628b4cba8a8c2a77c8e72279f2a1
URL:
https://github.com/llvm/llvm-project/commit/a25b6a1976cc628b4cba8a8c2a77c8e72279f2a1
DIFF:
https://github.com/llvm/llvm-project/commit/a25b6a1976cc628b4cba8a8c2a77c8e72279f2a1.di
arsenm wrote:
### Merge activity
* **Mar 7, 4:21 AM EST**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/130247).
https://github.com/llvm/llvm-project/pull/130247
__
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130068
>From f06e7f4a6b9638adc3ee286ce64191741e021d91 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 09:30:37 +
Subject: [PATCH] [CodeGen][NPM] Port RemoveLoadsIntoFakeUses to NPM
---
.../llvm/
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129866
>From 399b9973e9f788a58c7476925a85f090d673ca0f Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 10:34:25 +
Subject: [PATCH] [CodeGen][NPM] Port PatchableFunction to NPM
---
llvm/include/ll
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130070
>From dc9e5f0c8e37c54b7ba8fa24c57e8c8912861619 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 10:45:25 +
Subject: [PATCH] [CodeGen][NPM] Port StackFrameLayoutAnalysisPass to NPM
---
.../
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130071
>From e281c45b9e5853115605cd0c9fbb232b0dacdc3b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 10:56:28 +
Subject: [PATCH] [AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def
---
llvm/lib/Target
@@ -1239,6 +1239,12 @@ def FeatureXF32Insts : SubtargetFeature<"xf32-insts",
"v_mfma_f32_16x16x8_xf32 and v_mfma_f32_32x32x4_xf32"
>;
+def FeatureDynamicVGPR : SubtargetFeature <"dynamic-vgpr",
rovka wrote:
That's right, this is enabled from above the bac
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 147e7aff2a06c2b55dac8b9c9d1cd0c366325264
18645979e311d48be0926edac75cc92ed255fe5e --e
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 399b9973e9f788a58c7476925a85f090d673ca0f
9ba01338705902014ddf5f6d4285cd0563ce1e28 --e
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130069
>From 5c5dde0748e0ea175f51c462eae329bea3a9188e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 10:20:36 +
Subject: [PATCH] [CodeGen][NPM] Port MachineSanitizerBinaryMetadata to NPM
---
..
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130066
>From 1d23b9ce3735a442acdf3d1d2bae44cf81a9712c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:42:54 +
Subject: [PATCH] [CodeGen][NPM] Port PostRAHazardRecognizer to NPM
---
.../llvm/C
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130065
>From 18645979e311d48be0926edac75cc92ed255fe5e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:20:13 +
Subject: [PATCH] [AMDGPU][NPM] Port SIPreEmitPeephole to NPM
---
llvm/lib/Target/
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130064
>From 147e7aff2a06c2b55dac8b9c9d1cd0c366325264 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:07:23 +
Subject: [PATCH] [AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM
---
llvm/lib/Tar
rovka wrote:
> It seems to me this should be a separate attribute, it's not really part of
> the target
I don't really disagree with that. I think I made it a feature because it's
kind of a hardware mode (i.e. it takes over a CU, and waves that use dynamic
VGPRs can't be mixed with waves that
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130063
>From 33a5201fec71751cec72bf63fd80b873961ac247 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 05:26:49 +
Subject: [PATCH] [AMDGPU][NPM] Port SILateBranchLowering to NPM
---
llvm/lib/Targ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130062
>From 39768ea2dd18e37366c4034c677c83c1887fce0b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 04:52:38 +
Subject: [PATCH] [AMDGPU][NPM] Port SIInsertHardClauses to NPM
---
llvm/lib/Targe
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130061
>From 6faf91245f016f428516d571e5bc8c85f983eb53 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 04:41:08 +
Subject: [PATCH] [AMDGPU][NPM] Port SIInsertWaitcnts to NPM
---
llvm/lib/Target/A
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130059
>From 9ba01338705902014ddf5f6d4285cd0563ce1e28 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 10:52:00 +
Subject: [PATCH] [AMDGPU][NPM] Port GCNCreateVOPD to NPM
---
llvm/lib/Target/AMDG
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129857
>From 4b18d66c696656f0f04dff15028904f9b4c17901 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 09:19:08 +
Subject: [PATCH] [CodeGen][NPM] Port FEntryInserter to NPM
---
llvm/include/llvm/
https://github.com/arsenm commented:
It seems to me this should be a separate attribute, it's not really part of the
target
https://github.com/llvm/llvm-project/pull/130030
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@@ -511,6 +511,14 @@ SIRegisterInfo::getLargestLegalSuperClass(const
TargetRegisterClass *RC,
Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const SIFrameLowering *TFI = ST.getFrameLowering();
const SIMachineFunctionInfo *FuncInfo = MF.getInfo
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/127432
>From 7e29d6ace39058b631dcfff5533d8aee055de6dd Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Mon, 3 Mar 2025 12:25:13 +0900
Subject: [PATCH] obj2yaml
---
llvm/include/llvm/ObjectYAML/CovMap.h | 4
Author: Ricardo Jesus
Date: 2025-03-07T09:16:20Z
New Revision: 5a71fab0067bae0f532a6268749df71dbe66b4ac
URL:
https://github.com/llvm/llvm-project/commit/5a71fab0067bae0f532a6268749df71dbe66b4ac
DIFF:
https://github.com/llvm/llvm-project/commit/5a71fab0067bae0f532a6268749df71dbe66b4ac.diff
LOG:
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