[llvm-branch-commits] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

https://github.com/lukel97 approved this pull request. https://github.com/llvm/llvm-project/pull/94313 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2211,6 +,16 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector ) { if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) { RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional); +if (Fractional) { + unsigned ELEN =

[llvm-branch-commits] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/94313 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING:

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING:

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -1,5 +1,7 @@ # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v %s \ # RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x %s 2>&1 \ +# RUN:| FileCheck %s

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/lukel97 approved this pull request. Chiming in that this seems reasonable to me, given the performance impact of not having unaligned scalar accesses. And hopefully we can remove this one we're settled on a proper interface. https://github.com/llvm/llvm-project/pull/92143

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store( %passthru, ptr %p, , i64 } @llvm.riscv.vleff.nxv2i32(, ptr, i64) define @vpmerge_vleff( %passthru, ptr %p, %m, i32 zeroext %vl) { ; CHECK-LABEL: vpmerge_vleff: ; CHECK: # %bb.0: -; CHECK-NEXT:vsetvli zero,

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/lukel97 approved this pull request. https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/lukel97 commented: Removing it from vleNff sense to me. As long as we have the implicit-def $vl on the pseudo to prevent it being moved between vsetvlis I think it should be ok. https://github.com/llvm/llvm-project/pull/90049 ___

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/lukel97 approved this pull request. https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -;

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -146,16 +127,12 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v12 ; CHECK-NEXT: $v8 = VMV1R_V $v13 ; CHECK-NEXT: $v9 = VMV1R_V $v14 -; CHECK-NEXT: $v6 = VMV1R_V $v10 -; CHECK-NEXT: $v7 = VMV1R_V $v11 -; CHECK-NEXT: $v8 = VMV1R_V $v12 -;

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -146,16 +127,12 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v12 ; CHECK-NEXT: $v8 = VMV1R_V $v13 ; CHECK-NEXT: $v9 = VMV1R_V $v14 -; CHECK-NEXT: $v6 = VMV1R_V $v10 -; CHECK-NEXT: $v7 = VMV1R_V $v11 -; CHECK-NEXT: $v8 = VMV1R_V $v12 -;

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode< [RV32, RV64], [RegInfo<32,32,32>, RegInfo<64,64,64>]>; +class RISCVRegisterClass regTypes, int align, dag regList> +: RegisterClass<"RISCV", regTypes, align, regList> { + bit IsVRegClass = 0; +

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/lukel97 approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/lukel97 commented: Is this NFC? https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

lukel97 wrote: Superseded by #83856 https://github.com/llvm/llvm-project/pull/83848 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

https://github.com/lukel97 closed https://github.com/llvm/llvm-project/pull/83848 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

lukel97 wrote: > I think the "Requested by" comes from the git committer. There's a PR open to fix this: #82680 > @lukel97 i'm not sure if you have already or not, but it might be good to > include the recent test you added too. Sure thing, I can't see a way of editing/pushing more commits

[llvm-branch-commits] [llvm] Revert "[RISCV] Recurse on first operand of two operand shuffles (#79180)" (PR #80238)

https://github.com/lukel97 milestoned https://github.com/llvm/llvm-project/pull/80238 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Backport 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 to release/18.x (PR #79931)

https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/79931 This cherry picks a fix 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 for a miscompile (only with the -mrvv-vector-bits=zvl configuration or similar) introduced in bb8a8770e203ba027d141cd1200e93809ea66c8f, which is

[llvm-branch-commits] [llvm] [RISCV] Backport 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 to release/18.x (PR #79931)

https://github.com/lukel97 milestoned https://github.com/llvm/llvm-project/pull/79931 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] c0b9269 - [RISCV] Add helper to copy the AVL of another VSETVLIInfo. NFC

Author: Luke Lau Date: 2023-11-30T15:19:46+08:00 New Revision: c0b926939829d9d4bb6ac5825e62f30960b6ed22 URL: https://github.com/llvm/llvm-project/commit/c0b926939829d9d4bb6ac5825e62f30960b6ed22 DIFF: https://github.com/llvm/llvm-project/commit/c0b926939829d9d4bb6ac5825e62f30960b6ed22.diff