[llvm-branch-commits] [llvm] [RISCV] Add FeatureDisableLatencySchedHeuristic (PR #115858)

2024-11-27 Thread Michael Maitland via llvm-branch-commits
https://github.com/michaelmaitland approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

2024-11-26 Thread Michael Maitland via llvm-branch-commits
michaelmaitland wrote: I measured this patch on spec for an in-order and an out-of-order core. For the out-of-order core, 557.xz_r saw a regression. For the in-order core, I see regression on 456.hmmer and 458.sjeng. I saw no other significant improvements or regressions. These findings, comb

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

2024-11-12 Thread Michael Maitland via llvm-branch-commits
michaelmaitland wrote: For the recent scheduler patches, the common theme is we saw another target did something brought that functionality to RISC-V. How do we know that these changes are sensible defaults for RISC-V cores? Are you making measurements on any cores? Are they in order, out of o