[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt]; //===--===// let Predicates = [HasStdExtQ] in { - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in - def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt]; //===--===// let Predicates = [HasStdExtQ] in { - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in - def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

@@ -727,27 +728,49 @@ define void @buildvec_seq_v4i16_v2i32(ptr %x) { } define void @buildvec_vid_step1o2_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3, ptr %z4, ptr %z5, ptr %z6) { -; CHECK-LABEL: buildvec_vid_step1o2_v4i32: -; CHECK: # %bb.0: -; CHECK-NEXT:vsetivli zer

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

https://github.com/mshockwave approved this pull request. LGTM . I do have some minor questions but they're not blocking. https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://l

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

@@ -354,30 +354,51 @@ define @select_nxv32i32( %a, https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-comm

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

mshockwave wrote: > This helps reduce register pressure for some cases. Is it possible to provide some numbers to back this up? Preferably using some well known benchmarks like SPEC and/or llvm-test-suite https://github.com/llvm/llvm-project/pull/115858

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938) (PR #81953)

https://github.com/mshockwave approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/81953 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits