paschalis-mpeis wrote:
Yes, and that'd actually be better so we don't depend on whatever host GNU nm
the machine has.
Based on
[this](https://github.com/llvm/llvm-project/pull/135867#issuecomment-2841721288),
I'd say @aaupov intends to make this change too. I think he's away – let's see
what
paschalis-mpeis wrote:
Yeap, good idea. I could add `XFAIL` and modify runline like:
```
# RUN: link_fdata %s %t %t.patplt PREAGGPLT --synthetic --nmtool=llvm-nm
```
The differences would be :
- with `REQUIRES` we won't cross-run this x86 lit test on AArch64 (as I do
currently in ` #137831`)
-
paschalis-mpeis wrote:
That is perfect and the way we should go forward with this – thanks @yota9.
The problem is that the test is flaky: it passes on some systems but fails on
others.
Using`XFAIL` would make my AArch64 buildbot happy but it cause failures
(`Unexpectedly Passed`) on other AArc
paschalis-mpeis wrote:
Great. A quick way to use an llvm tool could be:
```bash
llvm-objdump -d -j .plt %t | grep @plt
```
This produces output similar to what `nm --synthetic` produces (when it works):
```bash
1430 :
```
You'll need ofc to tweak `link_fdata` to properly parse symb
paschalis-mpeis wrote:
Hey @yota9, thanks for the suggestions!
Indeed, the PLT entries exist in both binaries. For example running:
```
build/bin/llvm-objdump -d -j .plt
build/tools/bolt/test/X86/Output/callcont-fallthru.s.tmp
```
shows:
```
build/tools/bolt/test/X86/Output/callcont-fallth
paschalis-mpeis wrote:
Hey @yota9, thanks for the input. I tried something similar.
Even when I use `stub.c` and link it with:
```diff
-# RUN: %clang %cflags -fpic -shared -xc /dev/null -o %t.so
-## Link against a DSO to ensure PLT entries.
+# RUN: %clang %cflags %p/../Inputs/stub.c -fPIC -share
paschalis-mpeis wrote:
Hey folks, any updates on this?
I spent some time experimenting with @MaskRay's suggestion. I used a mock libc
shared object that had a `puts` symbol.
Indeed there won't be unresolved symbols now, however, still GNU `nm` doesn't
show a PLT entry when using `--synthetic`
paschalis-mpeis wrote:
Thanks a lot both! In case there's some delay in resolving this edge case, may
I suggest temporarily disabling this test on AArch64 until a more consistent
workaround is in place?
https://github.com/llvm/llvm-project/pull/135867
__
https://github.com/paschalis-mpeis commented:
Hey Amir,
Thanks for the PR. Unfortunately, it is still failing. The trick below doesn't
seem to work on my buildbot machine:
> Link against a DSO to ensure PLT entries.
So doing:
```bash
nm --synthetic callcont-fallthru.s.tmp
```
won't list a `pu
@@ -11,4 +11,4 @@ CHECK-SPE-NO-LBR: PERF2BOLT: Starting data aggregation job
RUN: perf record -e cycles -q -o %t.perf.data -- %t.exe
RUN: not perf2bolt -p %t.perf.data -o %t.perf.boltdata --spe %t.exe 2>&1 |
FileCheck %s --check-prefix=CHECK-SPE-LBR
-CHECK-SPE-LBR: PERF2BOLT-
@@ -197,6 +218,10 @@ void
BinarySection::flushPendingRelocations(raw_pwrite_stream &OS,
}
clearList(PendingRelocations);
+
+ if (SkippedPendingRelocations > 0)
+LLVM_DEBUG(dbgs() << "BOLT-INFO: Skipped " << SkippedPendingRelocations
+ << " pendin
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paschalis-mpeis wrote:
Thanks for your review Maksim.
Forced-push to rebase on top of #133085 and add commit b4e906c to address
reviewers.
https://github.com/llvm/llvm-project/pull/116964
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@@ -180,13 +178,16 @@ void DataAggregator::start() {
if (opts::ArmSPE) {
if (!opts::BasicAggregation) {
- errs() << "PERF2BOLT-ERROR: Arm SPE mode is combined only with "
-"BasicAggregation.\n";
- exit(1);
+ // pidfrom_ip to_ip
@@ -113,6 +153,37 @@ TEST_F(PerfSpeEventsTestHelper, SpeBranches) {
EXPECT_TRUE(checkEvents(1234, 10, {"branches-spe:"}));
}
+TEST_F(PerfSpeEventsTestHelper, SpeBranchesWithBrstack) {
+ // Check perf input with SPE branch events as brstack format.
+ // Example collection c
@@ -180,13 +178,16 @@ void DataAggregator::start() {
if (opts::ArmSPE) {
if (!opts::BasicAggregation) {
- errs() << "PERF2BOLT-ERROR: Arm SPE mode is combined only with "
-"BasicAggregation.\n";
- exit(1);
+ // pidfrom_ip to_ip
@@ -180,13 +178,16 @@ void DataAggregator::start() {
if (opts::ArmSPE) {
if (!opts::BasicAggregation) {
- errs() << "PERF2BOLT-ERROR: Arm SPE mode is combined only with "
-"BasicAggregation.\n";
- exit(1);
+ // pidfrom_ip to_ip
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paschalis-mpeis wrote:
I've put up a separate patch that makes Relocation type 32b and adds an
`Optional` field:
- #130792
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https://github.com/paschalis-mpeis commented:
Thanks a lot for your work Adam!
I commented on some changes and nits.
Also noting that for now this PR is stacked on top of #120741.
https://github.com/llvm/llvm-project/pull/129231
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@@ -88,6 +89,45 @@ struct PerfSpeEventsTestHelper : public testing::Test {
return SampleSize == DA.BasicSamples.size();
}
+
+ /// Compare LBREntries
+ bool checkLBREntry(const LBREntry &Lhs, const LBREntry &Rhs) {
+return Lhs.From == Rhs.From && Lhs.To == Rhs.To &&
@@ -88,6 +89,45 @@ struct PerfSpeEventsTestHelper : public testing::Test {
return SampleSize == DA.BasicSamples.size();
}
+
+ /// Compare LBREntries
+ bool checkLBREntry(const LBREntry &Lhs, const LBREntry &Rhs) {
+return Lhs.From == Rhs.From && Lhs.To == Rhs.To &&
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@@ -11,4 +11,4 @@ CHECK-SPE-NO-LBR: PERF2BOLT: Starting data aggregation job
RUN: perf record -e cycles -q -o %t.perf.data -- %t.exe
RUN: not perf2bolt -p %t.perf.data -o %t.perf.boltdata --spe %t.exe 2>&1 |
FileCheck %s --check-prefix=CHECK-SPE-LBR
-CHECK-SPE-LBR: PERF2BOLT-
@@ -1034,7 +1034,11 @@ ErrorOr DataAggregator::parseLBREntry() {
if (std::error_code EC = MispredStrRes.getError())
return EC;
StringRef MispredStr = MispredStrRes.get();
- if (MispredStr.size() != 1 ||
+ // SPE brstack mispredicted flags might be two characters long:
paschalis-mpeis wrote:
Hey Maksim,
Extending Relocations is even better. Thanks for the suggestion and the review.
Before proceeding, and regarding the size overheads, I want to highlight an
inconsistency with LLVM’s ObjectFile, where the type is 64 bits ([see
here](https://github.com/llvm/ll
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paschalis-mpeis wrote:
- force-push to stack this PR on top of #127812.
- add code & test to ensure that we skip pending relocations only when
`-force-patch` was set
https://github.com/llvm/llvm-project/pull/116964
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paschalis-mpeis wrote:
Forced-pushed to add the missing code. Also, this PR on now stacked top of
#123635.
Thanks for the comments @maks. I am not sure if your
[concern](https://github.com/llvm/llvm-project/issues/116817#issuecomment-2602866672)
on the issue still stands or not.
https://githu
@@ -165,11 +165,17 @@ void
BinarySection::flushPendingRelocations(raw_pwrite_stream &OS,
OS.pwrite(Patch.Bytes.data(), Patch.Bytes.size(),
SectionFileOffset + Patch.Offset);
+ uint64_t SkippedPendingRelocations = 0;
for (Relocation &Reloc : PendingReloca
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paschalis-mpeis wrote:
Rebased on top of the updated #96626
Thanks for suggesting `createReturnInstructionList`; I think it's better so I
used it.
https://github.com/llvm/llvm-project/pull/98448
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>From 2e9d663a9a164735fbe1a2408994acc1abaa8c21 Mon Sep 17 00:00:00 2001
From: Paschalis Mpeis
Date: Thu, 11 Jul 2024 09:32:12 +0100
Subject: [PATCH] [NFC][BOLT] Rename createDummyReturnFunction to
create
paschalis-mpeis wrote:
Thanks for your review @aaupov .
This is a stacked pull request as the updated docs refer to the
`-print-mappings` option.
So it will be merged after:
- #97567
https://github.com/llvm/llvm-project/pull/98162
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`createDummyReturnFunction` is not creating a function but instead only a
function body
that is simply a return statement.
This patch renames it to `createReturnBody`
>From b564185beebcd5d4d18036edfd2f1
https://github.com/paschalis-mpeis updated
https://github.com/llvm/llvm-project/pull/98162
>From f209cca87cf7c53242a353a505e3bfe34688a1b2 Mon Sep 17 00:00:00 2001
From: Paschalis Mpeis
Date: Tue, 9 Jul 2024 08:52:51 +0100
Subject: [PATCH 1/2] [BOLT] Added more details on heatmap docs.
---
bol
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Suggesting a few more details for Heatmaps.md
>From f209cca87cf7c53242a353a505e3bfe34688a1b2 Mon Sep 17 00:00:00 2001
From: Paschalis Mpeis
Date: Tue, 9 Jul 2024 08:52:51 +0100
Subject: [PATCH] [BOLT] Ad
https://github.com/paschalis-mpeis updated
https://github.com/llvm/llvm-project/pull/78432
>From a74ba110994e4535cd6c9206aa02d50503fb5577 Mon Sep 17 00:00:00 2001
From: Paschalis Mpeis
Date: Tue, 27 Feb 2024 15:00:28 +
Subject: [PATCH 1/7] [AArch64][TLI] Add TLI mappings for ArmPL modf, sin
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@@ -0,0 +1,52 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --filter "call.*(frexp|modf)" --version 4
+// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve -O3 -isystem
%S/../Headers/Inputs/include -mllvm -vector-library=ArmP
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paschalis-mpeis wrote:
The benefits of having`getFRemInstrCost` in my view are the below:
1. frem is a special case anyway:
It's an IR instruction that is not supported by all hw and targets have to
specialize.
Handling it in a dedicated switch case with a dedicated TTI function call,
clearly e
@@ -8362,9 +8362,20 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals,
unsigned OpIdx = isa(VL0) ? 0 : 1;
TTI::OperandValueInfo Op1Info = getOperandInfo(E->getOperand(0));
TTI::OperandValueInfo Op2Info = getOperandInfo(E->getOperand(OpIdx));
@@ -869,6 +870,18 @@ TargetTransformInfo::getOperandInfo(const Value *V) {
return {OpInfo, OpProps};
}
+InstructionCost TargetTransformInfo::getVecLibCallCost(
+const int OpCode, const TargetLibraryInfo *TLI, VectorType *VecTy,
+TTI::TargetCostKind CostKind) {
+ Typ
https://github.com/paschalis-mpeis updated
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>From 641aaf7c13d520bef52b092726f8346bfecb1c8d Mon Sep 17 00:00:00 2001
From: Paschalis Mpeis
Date: Wed, 21 Feb 2024 11:53:00 +
Subject: [PATCH 1/4] SLP cannot vectorize frem calls in AArch64.
It nee
paschalis-mpeis wrote:
Addressed reviewers and rebased to parent pr:
- #80423
Github is now rendering **only** the changes of this patch.
https://github.com/llvm/llvm-project/pull/82488
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@@ -8362,9 +8362,20 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals,
unsigned OpIdx = isa(VL0) ? 0 : 1;
TTI::OperandValueInfo Op1Info = getOperandInfo(E->getOperand(0));
TTI::OperandValueInfo Op2Info = getOperandInfo(E->getOperand(OpIdx));
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>From 641aaf7c13d520bef52b092726f8346bfecb1c8d Mon Sep 17 00:00:00 2001
From: Paschalis Mpeis
Date: Wed, 21 Feb 2024 11:53:00 +
Subject: [PATCH 1/3] SLP cannot vectorize frem calls in AArch64.
It nee
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Author: Paschalis Mpeis
Date: 2023-11-28T12:02:12Z
New Revision: 6f797921e23fe9a4500222e69ebd75aa7ba53ec1
URL:
https://github.com/llvm/llvm-project/commit/6f797921e23fe9a4500222e69ebd75aa7ba53ec1
DIFF:
https://github.com/llvm/llvm-project/commit/6f797921e23fe9a4500222e69ebd75aa7ba53ec1.diff
LO
Author: Paschalis Mpeis
Date: 2023-11-27T17:40:30Z
New Revision: cace1ec7346d3dfee9fcc5d67d79bce989b207d1
URL:
https://github.com/llvm/llvm-project/commit/cace1ec7346d3dfee9fcc5d67d79bce989b207d1
DIFF:
https://github.com/llvm/llvm-project/commit/cace1ec7346d3dfee9fcc5d67d79bce989b207d1.diff
LO
Author: Paschalis Mpeis
Date: 2023-11-24T16:49:05Z
New Revision: 21b30e18814016dc61b1a1ed87609e53454e3553
URL:
https://github.com/llvm/llvm-project/commit/21b30e18814016dc61b1a1ed87609e53454e3553
DIFF:
https://github.com/llvm/llvm-project/commit/21b30e18814016dc61b1a1ed87609e53454e3553.diff
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