wangpc-pp wrote:
Thanks @tstellar! Now all checks are passed!
https://github.com/llvm/llvm-project/pull/137490
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wangpc-pp wrote:
> This has some failing tests.
The failure is not related to this PR I think, it is about `compiler-rt/XRay`:
```
/var/lib/buildkite-agent/builds/linux-56-59b8f5d88-6vh59-1/llvm-project/github-pull-requests/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp:57:15:
error:
https://github.com/wangpc-pp updated
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wangpc-pp wrote:
> Is `users/wangpc-pp/spr/main.riscvnfc-use-bitmasks-generated-by-tablegen` the
> correct base branch?
Oh I forgot to say that this PR is stacked on #135599.
https://github.com/llvm/llvm-project/pull/135600
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https://github.com/llvm/llvm-project/pull/135600
So that we don't need to sync-up the table manually.
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/128146
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@@ -354,44 +353,38 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x
i64>, <8 x i64>} @load_
; RV32-NEXT:vmerge.vvm v20, v8, v16, v0
; RV32-NEXT:addi a1, sp, 16
; RV32-NEXT:vs4r.v v20, (a1) # Unknown-size Folded Spill
-; RV32-NEXT:vmv1r.v v0, v3
+; RV
@@ -403,236 +396,253 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8
x i64>, <8 x i64>} @load_
; RV32-NEXT:add a1, sp, a1
; RV32-NEXT:addi a1, a1, 16
; RV32-NEXT:vs8r.v v24, (a1) # Unknown-size Folded Spill
-; RV32-NEXT:vmv1r.v v0, v1
+; RV32-NEXT:
@@ -1891,31 +1886,44 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x
i1> %m, i32 zeroext %evl
; RV32-NEXT:addi a0, a0, 48
; RV32-NEXT:vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT:vand.vv v16, v24, v16, v0.t
-; RV32-NEXT:vsub.vv v24, v8,
@@ -16,6 +16,6 @@ body: |
$f1 = COPY %2
BLR8 implicit $lr8, implicit undef $rm, implicit $x3, implicit $f1
...
-# CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7
$vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31
$
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/118787
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wangpc-pp wrote:
> > Do you know what caused the X86 changes? I don't see any uses of
> > getRegPressureSetLimit in the X86 directory.
>
> Just checked line by line, I have no idea why X86 has some changes...
The reason may be mentally absorbing (and costed me a lot of time on
debugging...):
@@ -925,9 +925,16 @@ class TargetRegisterInfo : public MCRegisterInfo {
virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
/// Get the register unit pressure limit for this dimension.
- /// This limit must be adjusted dynamically for reserved registers.
+
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/118787
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https://github.com/wangpc-pp approved this pull request.
LGTM.
This fixes an existing bug reported by user.
https://github.com/llvm/llvm-project/pull/121175
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wangpc-pp wrote:
closed as it has been splitted into several small patches.
https://github.com/llvm/llvm-project/pull/119194
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https://github.com/llvm/llvm-project/pull/119194
>From b0d87f2a2e0ab0a13bdd85d5406451534e79ba8d Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Mon, 9 Dec 2024 19:18:06 +0800
Subject: [PATCH] Rewrite uses in AM/PPC targets
Created using spr 1.3.6-beta.1
wangpc-pp wrote:
> Why do we need #118787 if we can just update the passes to use
> RegisterClassInfo?
Because the APIs are messy and confusing, we don't know if there will be some
future users that use the raw limit directly.
https://github.com/llvm/llvm-project/pull/119194
_
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/119194
To reduce compile time.
This is a follow-up of #118787.
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wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/115843
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wangpc-pp wrote:
Thanks for evaluating this! The data is very helpful! @michaelmaitland
> Given @michaelmaitland's data, @wangpc-pp the burden shifts to you to clearly
> justify which cases this is profitable and figure out how to selectively
> enable only in profitable cases. I agree with @m
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
@@ -58,6 +58,19 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) {
return Info && Info->FastVectorUnalignedAccess;
}
+bool hasValidCPUModel(StringRef CPU) {
+ const CPUModel CPUModel = getCPUModel(CPU);
+ return CPUModel.MVendorID != 0 && CPUModel.MArchID != 0 &&
--
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/116745
None
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https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/116745
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@@ -22505,6 +22506,47 @@ Value
*CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
return nullptr;
}
+Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) {
+ const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef CPUStr = cast(CPUExpr)->getStri
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/115858
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@@ -22505,6 +22506,57 @@ Value
*CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
return nullptr;
}
+Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) {
+ const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef CPUStr = cast(CPUExpr)->getStri
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/2] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/3] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
clan
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/116231
We have defined `__riscv_cpu_model` variable in #101449. It contains
`mvendorid`, `marchid` and `mimpid` fields which are read via system
call `sys_riscv_hwprobe`.
We can support `__builtin_cpu_is` via compari
wangpc-pp wrote:
I added two experimental options: `-riscv-disable-latency-heuristic` and
`-riscv-should-track-lane-masks` and evaluated the statistics
(`regalloc.NumSpills`/`regalloc.NumReloads`) on llvm-test-suite (option: `-O3
-march=rva23u64`):
1. `-riscv-disable-latency-heuristic=true` an
wangpc-pp wrote:
Paste the data here as well
I added two experimental options: `-riscv-disable-latency-heuristic` and
`-riscv-should-track-lane-masks` and evaluated the statistics
(`regalloc.NumSpills`/`regalloc.NumReloads`) on llvm-test-suite (option: `-O3
-march=rva23u64`):
1. `-riscv
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/115858
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This helps reduce register pressure for some cases.
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@@ -23,11 +23,12 @@ define <8 x i32> @concat_2xv4i32(<4 x i32> %a, <4 x i32>
%b) {
define <8 x i32> @concat_4xv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2
x i32> %d) {
; VLA-LABEL: concat_4xv2i32:
; VLA: # %bb.0:
+; VLA-NEXT:vmv1r.v v12, v10
w
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/115843
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This can help to improve the register pressure for LMUL>1 cases.
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@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind
optsize {
;
; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a
@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind
optsize {
;
; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a
@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind
optsize {
;
; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/115162
We seem to forget these two instructions.
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@@ -2525,5 +2527,21 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
Options.LoadSizes = {8, 4, 2, 1};
else
Options.LoadSizes = {4, 2, 1};
+ if (IsZeroCmp && ST->hasVInstructions()) {
wangpc-pp wrote:
Good catch! I will
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
wangpc-pp wrote:
> > > > Can we break the enabling down into more manageable pieces? I think
> > > > `enableUnalignedScalarMem() && (Subtarget->hasStdExtZbb() ||
> > > > Subtarget->hasStdExtZbkb() || IsZeroCmp)` might be a good starting
> > > > point.
> > >
> > >
> > > I'd be fine with this
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/107548
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Ta
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/114971
We can convert non-power-of-2 types into extended value types
and then they will be widen.
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@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind
optsize {
; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT:addi sp, sp, -16
; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/114517
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https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/114517
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@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind
optsize {
; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT:addi sp, sp, -16
; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:
@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind
optsize {
; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT:addi sp, sp, -16
; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/114517
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@@ -1144,42 +2872,116 @@ entry:
define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind {
; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/114517
None
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wangpc-pp wrote:
Ping, any comment for current scalar part? I'm working on vector expansion and
will post it in a few days.
https://github.com/llvm/llvm-project/pull/107548
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https:
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp approved this pull request.
LGTM as it fixes a bug that exists for a long time.
https://github.com/llvm/llvm-project/pull/114089
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@@ -112,42 +104,46 @@ entry:
define i32 @bcmp_size_2(ptr %s1, ptr %s2) nounwind optsize {
; CHECK-ALIGNED-RV32-LABEL: bcmp_size_2:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -112,42 +104,46 @@ entry:
define i32 @bcmp_size_2(ptr %s1, ptr %s2) nounwind optsize {
; CHECK-ALIGNED-RV32-LABEL: bcmp_size_2:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
@@ -1144,42 +2872,116 @@ entry:
define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind {
; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/107548
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