[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/5] Reduce copies Created using spr 1.3.4 --- llvm/lib/Targe

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH 1/2] Fix wrong arguments Created using spr 1.3.4 --- llvm/lib

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH] Fix wrong arguments Created using spr 1.3.4 --- llvm/lib/Tar

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH] Fix wrong arguments Created using spr 1.3.4 --- llvm/lib/Tar

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/4] Reduce copies Created using spr 1.3.4 --- llvm/lib/Targe

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/3] Reduce copies Created using spr 1.3.4 --- llvm/lib/Targe

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/3] Reduce copies Created using spr 1.3.4 --- llvm/lib/Targe

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -146,16 +127,12 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v12 ; CHECK-NEXT: $v8 = VMV1R_V $v13 ; CHECK-NEXT: $v9 = VMV1R_V $v14 -; CHECK-NEXT: $v6 = VMV1R_V $v10 -; CHECK-NEXT: $v7 = VMV1R_V $v11 -; CHECK-NEXT: $v8 = VMV1R_V $v12 -; CHEC

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode< [RV32, RV64], [RegInfo<32,32,32>, RegInfo<64,64,64>]>; +class RISCVRegisterClass regTypes, int align, dag regList> +: RegisterClass<"RISCV", regTypes, align, regList> { + bit IsVRegClass = 0; + i

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode< [RV32, RV64], [RegInfo<32,32,32>, RegInfo<64,64,64>]>; +class RISCVRegisterClass regTypes, int align, dag regList> +: RegisterClass<"RISCV", regTypes, align, regList> { + bit IsVRegClass = 0; + i

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

wangpc-pp wrote: Committed as 4a6bc9fd14bd79f1edf5b651b43bd9bda9b90991. https://github.com/llvm/llvm-project/pull/85750 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/85750 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/85750 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/85750 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/85750 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/85750 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

wangpc-pp wrote: > > > JFYI, I don't find the AArch64 data particularly convincing for RISCV. > > > The magnitude of the change even on AArch64 is small, and could easily be > > > swung one direction or the other by differences in implementation between > > > the backends. > > > > > > Yeah!

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, wangpc-pp wrote: Most of the added pas

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/85750 We add a common class `SingleFusion` that accepts a single instruction pair to simplify fusion definitions. ___ llvm-branch-commits mailing list llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

wangpc-pp wrote: Ping. Any more concerns? https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH] Fix wrong arguments Created using spr 1.3.4 --- llvm/lib/Tar

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH] Fix wrong arguments Created using spr 1.3.4 --- llvm/lib/Tar

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/3] Reduce copies Created using spr 1.3.4 --- llvm/lib/Targe

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/2] Reduce copies Created using spr 1.3.4 --- llvm/lib/Targe

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH] Fix wrong arguments Created using spr 1.3.4 --- llvm/lib/Tar

[llvm-branch-commits] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/84894 This TSFlags was introduced by https://reviews.llvm.org/D108815. We store VLMul/NF into TSFlags and add helpers to get them. This can reduce some lines and I think there will be more usages. ___

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp ready_for_review https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH] Reduce copies Created using spr 1.3.4 --- llvm/lib/Target/RI

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -47,6 +48,15 @@ enum AtomicABI : unsigned { }; } // namespace RISCVAtomicAbiTag +namespace RISCVX3RegUse { +enum X3RegUsage : unsigned { + UNKNOWN = 0, + GP = 0, wangpc-pp wrote: Copy paste mistakes? Why all 0s? https://github.com/llvm/llvm-project/pull

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -24,6 +24,9 @@ .attribute priv_spec_revision, 0 # CHECK: attribute 12, 0 + wangpc-pp wrote: This blank should be added in Atomic ABI PR I think. https://github.com/llvm/llvm-project/pull/84598 ___ llvm-bran

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -520,3 +520,8 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; A6S: .attribute 14, 2 ; A6C: .attribute 14, 1 } + wangpc-pp wrote: No CHECKs for this test or I miss something here? https://github.com/llvm/llvm-project/pull/84598 ___

[llvm-branch-commits] [RISCV][NFC] Refactor copyPhysRegVector (PR #84455)

https://github.com/wangpc-pp converted_to_draft https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][NFC] Refactor copyPhysRegVector (PR #84455)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/84455 Reduce some duplications and make it easy to follow. We can optimize segment copies later. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/84448 The opcode will be determined by LMUL. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-

[llvm-branch-commits] [llvm] release/18.x: [TableGen] Fix wrong codegen of BothFusionPredicateWithMCInstPredicate (#83990) (PR #83999)

wangpc-pp wrote: Ping? https://github.com/llvm/llvm-project/pull/83999 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, wangpc-pp wrote: @topperc WDYT? https

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, wangpc-pp wrote: Yeah, this point make

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, wangpc-pp wrote: We have already disab

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/80124 >From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001 From: wangpc Date: Sun, 18 Feb 2024 11:12:16 +0800 Subject: [PATCH 1/2] Move after addIRPasses Created using spr 1.3.4 --- llvm/lib/Targ

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

wangpc-pp wrote: Gentle ping. https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

wangpc-pp wrote: Commited as b8ed69ecc01385c03844e8fa05ba418a5670d322. SPR sometines failed to land after rebasing: ```shell # spr land --cherry-pick

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322 >From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 20 Feb 2024 18:20:03 +0800 Subject: [PATCH 1/2] Fix typo and address comments Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322 >From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 20 Feb 2024 18:20:03 +0800 Subject: [PATCH] Fix typo and address comments Created using spr 1.3.4 --- ll

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322 >From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 20 Feb 2024 18:20:03 +0800 Subject: [PATCH] Fix typo and address comments Created using spr 1.3.4 --- ll

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322 >From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 20 Feb 2024 18:20:03 +0800 Subject: [PATCH] Fix typo and address comments Created using spr 1.3.4 --- ll

[llvm-branch-commits] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/82322 This intrinsic was introduced by #81331, which is a lot like `llvm.readcyclecounter`. For the RISCV implementation, we rename `ReadCycleWide` pseudo to `ReadCounterWide` and make it accept two operands (the low

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/80124 >From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001 From: wangpc Date: Sun, 18 Feb 2024 11:12:16 +0800 Subject: [PATCH] Move after addIRPasses Created using spr 1.3.4 --- llvm/lib/Target/R

[llvm-branch-commits] [Clang][RISCV] Refactor builtins to TableGen (PR #80280)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/80280 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [libcxx] [flang] [llvm] [libc] [compiler-rt] [RISCV] Support select optimization (PR #80124)

wangpc-pp wrote: > JFYI, I don't find the AArch64 data particularly convincing for RISCV. The > magnitude of the change even on AArch64 is small, and could easily be swung > one direction or the other by differences in implementation between the > backends. Yeah! The result will differ for di

[llvm-branch-commits] [clang] [Clang][RISCV] Refactor builtins to TableGen (PR #80280)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/80280 This mechanism is introduced by #68324. This refactor makes the prototype and attributes clear. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm

[llvm-branch-commits] [compiler-rt] [llvm] [clang] [libc] [libcxx] [flang] [RISCV] Support select optimization (PR #80124)

@@ -0,0 +1,873 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -select-optimize -mtriple=riscv64 -S < %s \ +; RUN: | FileCheck %s --check-prefix=CHECK-SELECT +; RUN: opt -select-optimize -mtriple=riscv64 -mattr=+enable-select-opt -S < %s

[llvm-branch-commits] [compiler-rt] [llvm] [clang] [libc] [libcxx] [flang] [RISCV] Support select optimization (PR #80124)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [compiler-rt] [llvm] [flang] [libcxx] [libc] [RISCV] Support select optimization (PR #80124)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [compiler-rt] [clang] [lldb] [flang] [clang-tools-extra] [lld] [libcxxabi] [libcxx] [libc] [SelectOpt] Print instruction instead of pointer (PR #80125)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/80125 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang-tools-extra] [libcxx] [libcxxabi] [libc] [flang] [llvm] [lldb] [clang] [compiler-rt] [lld] [SelectOpt] Print instruction instead of pointer (PR #80125)

wangpc-pp wrote: Committed as 995d21bc6ff2220b2887cf9640d936eb99b3c617. Somehow `spr` failed with error so I have to land it manually: ``` #️⃣ Pull Request #80125

[llvm-branch-commits] [flang] [clang] [libcxx] [libc] [compiler-rt] [llvm] [RISCV] Support select optimization (PR #80124)

wangpc-pp wrote: > > and the measurement data still stands for RISCV. > > Please give the measurement data in this review or a direct link to it. I > tried searching for it, and did not immediately find it. It's in the Phabricator link (https://reviews.llvm.org/D138990): > The headline numbe

[llvm-branch-commits] [llvm] [clang-tools-extra] [flang] [libcxx] [lldb] [libcxxabi] [libc] [compiler-rt] [lld] [clang] [SelectOpt] Print instruction instead of pointer (PR #80125)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/80125 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libcxx] [llvm] [clang] [clang-tools-extra] [lld] [flang] [libc] [compiler-rt] [libcxxabi] [lldb] [SelectOpt] Print instruction instead of pointer (PR #80125)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/80125 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [flang] [libc] [libcxx] [compiler-rt] [clang] [RISCV] Support select optimization (PR #80124)

@@ -0,0 +1,873 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -select-optimize -mtriple=riscv64 -S < %s \ +; RUN: | FileCheck %s --check-prefix=CHECK-SELECT +; RUN: opt -select-optimize -mtriple=riscv64 -mattr=+enable-select-opt -S < %s

[llvm-branch-commits] [flang] [libc] [libcxx] [clang] [llvm] [compiler-rt] [SelectOpt] Print instruction instead of pointer (PR #80125)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/80125 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libcxx] [libc] [flang] [llvm] [clang] [compiler-rt] [RISCV] Support select optimization (PR #80124)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/80124 AArch64 has enabled this in https://reviews.llvm.org/D138990, and the measurement data still stands for RISCV. And, similar optimization like #77284 is added too.

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79425 (PR #79560)

https://github.com/wangpc-pp approved this pull request. LGTM. (Is this the right approach in current workflow?) https://github.com/llvm/llvm-project/pull/79560 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.

[llvm-branch-commits] Revert "[RISCV] Make X5 allocatable for JALR on CPUs without RAS" (PR #78946)

wangpc-pp wrote: Sorry for the noise, this is for testing spr tools. https://github.com/llvm/llvm-project/pull/78946 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-com

[llvm-branch-commits] Revert "[RISCV] Make X5 allocatable for JALR on CPUs without RAS" (PR #78946)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/78946 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] Revert "[RISCV] Make X5 allocatable for JALR on CPUs without RAS" (PR #78946)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/78946 This reverts commit 333963a9c75b2f79bff73227eae0c72747ac945e. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin