[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Craig Topper via llvm-branch-commits
@@ -11724,13 +11726,27 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, Results.push_back(Result); break; } - case ISD::READCYCLECOUNTER: { -assert(!Subtarget.is64Bit() && - "READCYCLECOUNTER only has custom type legalization on riscv32"); +

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Craig Topper via llvm-branch-commits
@@ -363,7 +365,7 @@ def CSRSystemRegister : AsmOperandClass { let DiagnosticType = "InvalidCSRSystemRegister"; } -def csr_sysreg : RISCVOp { +def csr_sysreg : RISCVOp, ImmLeaf(Imm);"> { topperc wrote: TImmLeaf https://github.com/llvm/llvm-project/pull/8232

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Craig Topper via llvm-branch-commits
@@ -126,9 +126,10 @@ enum NodeType : unsigned { // Floating point fmax and fmin matching the RISC-V instruction semantics. FMAX, FMIN, - // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target - // (returns (Lo, Hi)). It takes a chain operand. - READ_CYCL

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Wang Pengcheng via llvm-branch-commits
wangpc-pp wrote: Commited as b8ed69ecc01385c03844e8fa05ba418a5670d322. SPR sometines failed to land after rebasing: ```shell # spr land --cherry-pick

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Wang Pengcheng via llvm-branch-commits
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Wang Pengcheng via llvm-branch-commits
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322 >From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 20 Feb 2024 18:20:03 +0800 Subject: [PATCH 1/2] Fix typo and address comments Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Fangrui Song via llvm-branch-commits
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Fangrui Song via llvm-branch-commits
@@ -126,9 +126,9 @@ enum NodeType : unsigned { // Floating point fmax and fmin matching the RISC-V instruction semantics. FMAX, FMIN, - // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target + // READ_COUNTER_WIDE - A read of the 64-bit counter CSR on a 3

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Wang Pengcheng via llvm-branch-commits
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322 >From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 20 Feb 2024 18:20:03 +0800 Subject: [PATCH] Fix typo and address comments Created using spr 1.3.4 --- ll

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Wang Pengcheng via llvm-branch-commits
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322 >From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 20 Feb 2024 18:20:03 +0800 Subject: [PATCH] Fix typo and address comments Created using spr 1.3.4 --- ll

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Alex Bradbury via llvm-branch-commits
https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Joseph Huber via llvm-branch-commits
https://github.com/jhuber6 approved this pull request. https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Wang Pengcheng via llvm-branch-commits
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

2024-02-20 Thread Wang Pengcheng via llvm-branch-commits
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322 >From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 20 Feb 2024 18:20:03 +0800 Subject: [PATCH] Fix typo and address comments Created using spr 1.3.4 --- ll