Author: Weihang Fan Date: 2024-05-14T14:13:35-07:00 New Revision: 47b6dc45e39aea5369308c602f0d6341a054aca2
URL: https://github.com/llvm/llvm-project/commit/47b6dc45e39aea5369308c602f0d6341a054aca2 DIFF: https://github.com/llvm/llvm-project/commit/47b6dc45e39aea5369308c602f0d6341a054aca2.diff LOG: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) In DAGCombiner, the `performCONDCombine` function attempts to remove AND instructions in front of SUBS (cmp) instructions for which the AND is transparent. The rules for that are correct, but it fails to take into account the case where the SUBS instruction has multiple users with different condition codes for comparison and simply removes the AND for all of them. This causes a miscompilation in the attached test case. (cherry picked from commit 72eaa0ed9934bfaa2449091bbc6e45648d1396d6) Added: Modified: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/test/CodeGen/AArch64/and-mask-removal.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 95d8ab95b2c09..bcfd0253e73c8 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -22122,7 +22122,8 @@ SDValue performCONDCombine(SDNode *N, SDNode *SubsNode = N->getOperand(CmpIndex).getNode(); unsigned CondOpcode = SubsNode->getOpcode(); - if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0)) + if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0) || + !SubsNode->hasOneUse()) return SDValue(); // There is a SUBS feeding this condition. Is it fed by a mask we can diff --git a/llvm/test/CodeGen/AArch64/and-mask-removal.ll b/llvm/test/CodeGen/AArch64/and-mask-removal.ll index 17ff015970168..a31355549ba87 100644 --- a/llvm/test/CodeGen/AArch64/and-mask-removal.ll +++ b/llvm/test/CodeGen/AArch64/and-mask-removal.ll @@ -526,4 +526,26 @@ define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) { ret i64 %4 } +define i64 @test_2_selects(i8 zeroext %a) { +; CHECK-LABEL: test_2_selects: +; CHECK: ; %bb.0: +; CHECK-NEXT: add w9, w0, #24 +; CHECK-NEXT: mov w8, #131 +; CHECK-NEXT: and w9, w9, #0xff +; CHECK-NEXT: cmp w9, #81 +; CHECK-NEXT: mov w9, #57 +; CHECK-NEXT: csel x8, x8, xzr, lo +; CHECK-NEXT: csel x9, xzr, x9, eq +; CHECK-NEXT: add x0, x8, x9 +; CHECK-NEXT: ret + %1 = add i8 %a, 24 + %2 = zext i8 %1 to i64 + %3 = icmp ult i8 %1, 81 + %4 = select i1 %3, i64 131, i64 0 + %5 = icmp eq i8 %1, 81 + %6 = select i1 %5, i64 0, i64 57 + %7 = add i64 %4, %6 + ret i64 %7 +} + declare i8 @llvm.usub.sat.i8(i8, i8) #0 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
