https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109410
>From 831b4a6dde281d7cd3b95557c15cb417d278d568 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 13:57:14 +0400
Subject: [PATCH 1/2] AMDGPU: Custom expand flat cmpxchg which may access
private
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/102599
>From a2719d4938a1eaf135c275257b1b6c0318ccc801 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 9 Aug 2024 14:51:41 +0400
Subject: [PATCH] AMDGPU: Add noalias.addrspace metadata when autoupgrading
atomic
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109408
>From caecd58b94c52b5568fc0014dad1c51796e4d36e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 12 Sep 2024 12:44:04 +0400
Subject: [PATCH] AMDGPU: Add baseline tests for cmpxchg custom expansion
We need
Author: Abhishek Varma
Date: 2024-09-30T14:51:23+05:30
New Revision: b3cdd66549a17e8ab83b23117d0a1fc9feb50534
URL:
https://github.com/llvm/llvm-project/commit/b3cdd66549a17e8ab83b23117d0a1fc9feb50534
DIFF:
https://github.com/llvm/llvm-project/commit/b3cdd66549a17e8ab83b23117d0a1fc9feb50534.diff
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/110470
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/110470
Backport e9d12a6b451bd403d95105aa976a011dc821f126
83fe85115da9dc25fa270d2ea8140113c8d49670
Requested by: @arsenm
>From 4477e7b862c603da7586598248e4ea0c60c81407 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
D
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: None (llvmbot)
Changes
Backport e9d12a6b451bd403d95105aa976a011dc821f126
83fe85115da9dc25fa270d2ea8140113c8d49670
Requested by: @arsenm
---
Patch is 29.90 KiB, truncated to 20.00 KiB below, full version:
https://github.com/ll
llvmbot wrote:
@jayfoad @arsenm What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/110470
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/110470
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@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-O
https://github.com/jayfoad approved this pull request.
https://github.com/llvm/llvm-project/pull/110470
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/110256
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Author: David Truby
Date: 2024-09-30T17:26:07+01:00
New Revision: 00e4f81a294e8e2d78d572c76dd017a8af050cf0
URL:
https://github.com/llvm/llvm-project/commit/00e4f81a294e8e2d78d572c76dd017a8af050cf0
DIFF:
https://github.com/llvm/llvm-project/commit/00e4f81a294e8e2d78d572c76dd017a8af050cf0.diff
L
https://github.com/agozillon approved this pull request.
LGTM, @TIFitis would be a good secondary reviewer if he wishes to do so!
https://github.com/llvm/llvm-project/pull/109810
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h
https://github.com/agozillon edited
https://github.com/llvm/llvm-project/pull/109810
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https://github.com/mjklemm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/110266
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https://github.com/skatrak updated
https://github.com/llvm/llvm-project/pull/109810
>From f61e3a60d6f494d08b58ded9b802f2b3d92b728f Mon Sep 17 00:00:00 2001
From: Sergio Afonso
Date: Fri, 20 Sep 2024 17:11:34 +0100
Subject: [PATCH] [MLIR][OpenMP] Use map format to represent
use_device_{addr,ptr
https://github.com/skatrak updated
https://github.com/llvm/llvm-project/pull/110266
>From d6920f4bd10cdf88d6d640f8e1da2c595c39bdb6 Mon Sep 17 00:00:00 2001
From: Sergio Afonso
Date: Thu, 26 Sep 2024 11:42:03 +0100
Subject: [PATCH] [MLIR][OpenMP] Improve omp.section block arguments handling
The
https://github.com/skatrak updated
https://github.com/llvm/llvm-project/pull/109811
>From a821f44e2c9ac732c752abae62385c4d78082a2b Mon Sep 17 00:00:00 2001
From: Sergio Afonso
Date: Tue, 24 Sep 2024 15:40:17 +0100
Subject: [PATCH] [MLIR][OpenMP] Document entry block argument-defining clauses
(
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/110490
Backport 81ba95cefe1b5a12f0a7d8e6a383bcce9e95b785
Requested by: @arsenm
>From 2c0b211043d4516fa33c1a87c0e239f4de58b4fc Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 30 Sep 2024 13:43:53 +0400
Subjec
https://github.com/llvmbot milestoned
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llvmbot wrote:
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Author: None (llvmbot)
Changes
Backport 81ba95cefe1b5a12f0a7d8e6a383bcce9e95b785
Requested by: @arsenm
---
Full diff: https://github.com/llvm/llvm-project/pull/110490.diff
4 Files Affected:
- (modified) llvm/include/llvm/CodeGen/FastISel
llvmbot wrote:
@llvm/pr-subscribers-llvm-selectiondag
Author: None (llvmbot)
Changes
Backport 81ba95cefe1b5a12f0a7d8e6a383bcce9e95b785
Requested by: @arsenm
---
Full diff: https://github.com/llvm/llvm-project/pull/110490.diff
4 Files Affected:
- (modified) llvm/include/llvm/CodeGen/Fa
llvmbot wrote:
@nikic What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/110490
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@@ -10616,19 +10616,43 @@ SDValue SITargetLowering::LowerFDIV16(SDValue Op,
SelectionDAG &DAG) const {
return FastLowered;
SDLoc SL(Op);
- SDValue Src0 = Op.getOperand(0);
- SDValue Src1 = Op.getOperand(1);
-
- SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f
@@ -4903,16 +4903,40 @@ bool AMDGPULegalizerInfo::legalizeFDIV16(MachineInstr
&MI,
LLT S16 = LLT::scalar(16);
LLT S32 = LLT::scalar(32);
+ // a32.u = opx(V_CVT_F32_F16, a.u); // CVT to F32
+ // b32.u = opx(V_CVT_F32_F16, b.u); // CVT to F32
+ // r32.u = opx(V_RCP_F32,
skatrak wrote:
Ping for review!
https://github.com/llvm/llvm-project/pull/109810
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@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_s
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/110108
>From 92eb911fcd781825fa88aaec6c05b9484f49d158 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Wed, 25 Sep 2024 16:16:29 +0300
Subject: [PATCH] [AArch64] Generalize the instruction size checking in
https://github.com/tblah approved this pull request.
Thanks!
https://github.com/llvm/llvm-project/pull/110266
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https://github.com/skatrak updated
https://github.com/llvm/llvm-project/pull/110267
>From 2c5d74d932797b916b5f0da6fb017b5f4af2b2b4 Mon Sep 17 00:00:00 2001
From: Sergio Afonso
Date: Fri, 27 Sep 2024 13:51:27 +0100
Subject: [PATCH] [Flang][OpenMP] Improve entry block argument creation and
bindi
@@ -3614,3 +3614,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
arsenm wrote:
probably should just be const char*, this will probably only ever be used with
literals
https://github.com/llvm/l
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
f
@@ -1628,6 +1628,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (co
@@ -1628,6 +1628,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (co
@@ -1628,6 +1628,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
arsenm wrote:
No auto, no reference. This is
atrosinenko wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/110108?utm_source=stack-comment-downstack-mergeability-warni
https://github.com/zero9178 approved this pull request.
https://github.com/llvm/llvm-project/pull/110419
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https://github.com/llvm/llvm-project/pull/110567
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@@ -285,7 +285,75 @@ argument's type:
specific `mlir::Attribute` subclass) will be used instead.
- Other attribute types will be represented with their `storageType`.
- It will create `Operands` structure for each operation, which is an
-empty structure subclassing all oper
@@ -285,7 +285,75 @@ argument's type:
specific `mlir::Attribute` subclass) will be used instead.
- Other attribute types will be represented with their `storageType`.
- It will create `Operands` structure for each operation, which is an
-empty structure subclassing all oper
https://github.com/bhandarkar-pranav edited
https://github.com/llvm/llvm-project/pull/109811
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https://github.com/bhandarkar-pranav commented:
LGTM. Given how reviewing docs essentially turns into a series of subjective
opinions or preferences, please consider most all of my comments as nits,
except the one about alphabetical sorting of clauses.
https://github.com/llvm/llvm-project/pull
@@ -285,7 +285,75 @@ argument's type:
specific `mlir::Attribute` subclass) will be used instead.
- Other attribute types will be represented with their `storageType`.
- It will create `Operands` structure for each operation, which is an
-empty structure subclassing all oper
@@ -285,7 +285,75 @@ argument's type:
specific `mlir::Attribute` subclass) will be used instead.
- Other attribute types will be represented with their `storageType`.
- It will create `Operands` structure for each operation, which is an
-empty structure subclassing all oper
@@ -285,7 +285,75 @@ argument's type:
specific `mlir::Attribute` subclass) will be used instead.
- Other attribute types will be represented with their `storageType`.
- It will create `Operands` structure for each operation, which is an
-empty structure subclassing all oper
Author: Yingwei Zheng
Date: 2024-10-01T08:51:27+02:00
New Revision: a7554dfc222b13624426ebd6ef46e122b9c16ee7
URL:
https://github.com/llvm/llvm-project/commit/a7554dfc222b13624426ebd6ef46e122b9c16ee7
DIFF:
https://github.com/llvm/llvm-project/commit/a7554dfc222b13624426ebd6ef46e122b9c16ee7.diff
Author: hev
Date: 2024-10-01T08:51:27+02:00
New Revision: 99058521d4c80635f60b2c1442b683395e0ee818
URL:
https://github.com/llvm/llvm-project/commit/99058521d4c80635f60b2c1442b683395e0ee818
DIFF:
https://github.com/llvm/llvm-project/commit/99058521d4c80635f60b2c1442b683395e0ee818.diff
LOG: [Loo
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/109125
>From a7554dfc222b13624426ebd6ef46e122b9c16ee7 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 10 Sep 2024 09:19:39 +0800
Subject: [PATCH 1/2] [LoongArch][ISel] Check the number of sign bits in
`PatGprGpr_3
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/109125
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@@ -2546,6 +2510,7 @@ void AArch64AsmPrinter::emitInstruction(const
MachineInstr *MI) {
TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
TLSDescCall.addOperand(Sym);
EmitToStreamer(*OutStreamer, TLSDescCall);
+--InstsEmitted; // no code emitted
dav
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/109915
>From b3734d9f93c1f8d908836a966f77c6792242df99 Mon Sep 17 00:00:00 2001
From: Weining Lu
Date: Mon, 19 Aug 2024 16:51:21 +0800
Subject: [PATCH] [LoongArch] Fix the assertion for atomic store with 'ptr'
type
(cherry
Author: Weining Lu
Date: 2024-10-01T08:53:44+02:00
New Revision: b3734d9f93c1f8d908836a966f77c6792242df99
URL:
https://github.com/llvm/llvm-project/commit/b3734d9f93c1f8d908836a966f77c6792242df99
DIFF:
https://github.com/llvm/llvm-project/commit/b3734d9f93c1f8d908836a966f77c6792242df99.diff
LO
Martin =?utf-8?q?Storsjö?= ,
Martin =?utf-8?q?Storsjö?= ,
Martin =?utf-8?q?Storsjö?=
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ht
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/109915
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Author: Petar Avramovic
Date: 2024-10-01T08:56:50+02:00
New Revision: 962edd3f71eebdcd781222cdd97a561979894003
URL:
https://github.com/llvm/llvm-project/commit/962edd3f71eebdcd781222cdd97a561979894003
DIFF:
https://github.com/llvm/llvm-project/commit/962edd3f71eebdcd781222cdd97a561979894003.dif
Author: Petar Avramovic
Date: 2024-10-01T08:56:50+02:00
New Revision: 03d133728ae14704b262c55bbb72ecd9d048add5
URL:
https://github.com/llvm/llvm-project/commit/03d133728ae14704b262c55bbb72ecd9d048add5
DIFF:
https://github.com/llvm/llvm-project/commit/03d133728ae14704b262c55bbb72ecd9d048add5.dif
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/110470
>From 03d133728ae14704b262c55bbb72ecd9d048add5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 30 Sep 2024 10:39:17 +0200
Subject: [PATCH 1/2] AMDGPU: Add test for 16 bit unsigned scratch offsets
(#110255)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/110263
>From 53010fcf66b5a84153bce6b7e866edb596e59cf4 Mon Sep 17 00:00:00 2001
From: Louis Dionne
Date: Fri, 27 Sep 2024 08:53:02 -0400
Subject: [PATCH] [libc++] Fix AppleClang version number when checking for
__builtin_ve
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/110263
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Author: Louis Dionne
Date: 2024-10-01T08:56:18+02:00
New Revision: 53010fcf66b5a84153bce6b7e866edb596e59cf4
URL:
https://github.com/llvm/llvm-project/commit/53010fcf66b5a84153bce6b7e866edb596e59cf4
DIFF:
https://github.com/llvm/llvm-project/commit/53010fcf66b5a84153bce6b7e866edb596e59cf4.diff
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/110470
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https://github.com/tru closed https://github.com/llvm/llvm-project/pull/109093
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tru wrote:
Sounds to me like we don't have to accept this patch into the 19.1 release.
Please re-open and argue if you don't agree with that assesment.
https://github.com/llvm/llvm-project/pull/109093
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h
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/107184
>From 149bfdd61c961edbf49c2ea7fadf9d3c1a79a55e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Wed, 4 Sep 2024 12:19:46 +0800
Subject: [PATCH] [Clang][CodeGen] Fix type for atomic float incdec operators
(#107075)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/110259
>From be879942edbb27b4a43eb6b5f4162153972fc41a Mon Sep 17 00:00:00 2001
From: David Spickett
Date: Thu, 15 Aug 2024 08:14:13 +
Subject: [PATCH 1/2] [lldb][test] Mark sys_info zdump test unsupported on 32
bit Arm
github-actions[bot] wrote:
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https://github.com/tru closed https://github.com/llvm/llvm-project/pull/110162
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https://github.com/tru closed https://github.com/llvm/llvm-project/pull/107184
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Martin =?utf-8?q?Storsjö?= ,
Martin =?utf-8?q?Storsjö?= ,
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https://github.com/tru updated https://github.com/llvm/llvm-project/pull/109865
>From 7d1f2065d68795b6fc6de4953f9f0ac719cf1c65 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Storsj=
Author: Martin Storsjö
Date: 2024-10-01T08:53:03+02:00
New Revision: 7d1f2065d68795b6fc6de4953f9f0ac719cf1c65
URL:
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DIFF:
https://github.com/llvm/llvm-project/commit/7d1f2065d68795b6fc6de4953f9f0ac719cf1c65.diff
Author: Martin Storsjö
Date: 2024-10-01T08:53:03+02:00
New Revision: a0fc8a2b2b85a70c8c523ff2d1fe4ef2e86cda7f
URL:
https://github.com/llvm/llvm-project/commit/a0fc8a2b2b85a70c8c523ff2d1fe4ef2e86cda7f
DIFF:
https://github.com/llvm/llvm-project/commit/a0fc8a2b2b85a70c8c523ff2d1fe4ef2e86cda7f.diff
Author: Martin Storsjö
Date: 2024-10-01T08:53:03+02:00
New Revision: 2b6c23303f7c3f6397003cdac4be6e9e6b78d957
URL:
https://github.com/llvm/llvm-project/commit/2b6c23303f7c3f6397003cdac4be6e9e6b78d957
DIFF:
https://github.com/llvm/llvm-project/commit/2b6c23303f7c3f6397003cdac4be6e9e6b78d957.diff
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/109624
>From aaa7027716ad347cda75865e99a2ff654bed6bf1 Mon Sep 17 00:00:00 2001
From: Nikita Popov
Date: Fri, 20 Sep 2024 16:57:46 +0200
Subject: [PATCH] [LoopPeel] Fix LCSSA phi node invalidation
In the test case, the BECo
Author: Nikita Popov
Date: 2024-10-01T08:52:08+02:00
New Revision: aaa7027716ad347cda75865e99a2ff654bed6bf1
URL:
https://github.com/llvm/llvm-project/commit/aaa7027716ad347cda75865e99a2ff654bed6bf1
DIFF:
https://github.com/llvm/llvm-project/commit/aaa7027716ad347cda75865e99a2ff654bed6bf1.diff
github-actions[bot] wrote:
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ht
Author: Martin Storsjö
Date: 2024-10-01T08:53:03+02:00
New Revision: 997b66e566886b8a395b852db46e7930f757b818
URL:
https://github.com/llvm/llvm-project/commit/997b66e566886b8a395b852db46e7930f757b818
DIFF:
https://github.com/llvm/llvm-project/commit/997b66e566886b8a395b852db46e7930f757b818.diff
Martin =?utf-8?q?Storsj=C3=B6?= ,
Martin =?utf-8?q?Storsj=C3=B6?= ,
Martin =?utf-8?q?Storsj=C3=B6?=
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https://github.com/tru closed https://github.com/llvm/llvm-project/pull/109865
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https://github.com/tru closed https://github.com/llvm/llvm-project/pull/109624
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Author: Yingwei Zheng
Date: 2024-10-01T08:47:00+02:00
New Revision: 149bfdd61c961edbf49c2ea7fadf9d3c1a79a55e
URL:
https://github.com/llvm/llvm-project/commit/149bfdd61c961edbf49c2ea7fadf9d3c1a79a55e
DIFF:
https://github.com/llvm/llvm-project/commit/149bfdd61c961edbf49c2ea7fadf9d3c1a79a55e.diff
Author: Princeton Ferro
Date: 2024-10-01T08:47:51+02:00
New Revision: b3731b36421e23737be2b4785700267b96c3241f
URL:
https://github.com/llvm/llvm-project/commit/b3731b36421e23737be2b4785700267b96c3241f
DIFF:
https://github.com/llvm/llvm-project/commit/b3731b36421e23737be2b4785700267b96c3241f.dif
github-actions[bot] wrote:
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https://github.com/tru updated https://github.com/llvm/llvm-project/pull/108397
>From b3731b36421e23737be2b4785700267b96c3241f Mon Sep 17 00:00:00 2001
From: Princeton Ferro
Date: Wed, 4 Sep 2024 07:18:53 -0700
Subject: [PATCH] [DAGCombiner] cache negative result from
getMergeStoreCandidates()
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/108397
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Author: Louis Dionne
Date: 2024-09-26T16:00:43-04:00
New Revision: 8a25c601eb64bcdb7c6c74bee52655468dfdd91b
URL:
https://github.com/llvm/llvm-project/commit/8a25c601eb64bcdb7c6c74bee52655468dfdd91b
DIFF:
https://github.com/llvm/llvm-project/commit/8a25c601eb64bcdb7c6c74bee52655468dfdd91b.diff
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/109920
>From 8679d1b51bd91d638ac3babba03a404e4031f9ea Mon Sep 17 00:00:00 2001
From: Timothy Pearson <162513562+tpearson-...@users.noreply.github.com>
Date: Wed, 25 Sep 2024 02:09:50 -0500
Subject: [PATCH] [SDAG] Honor signe
Author: Timothy Pearson
Date: 2024-10-01T08:55:02+02:00
New Revision: 8679d1b51bd91d638ac3babba03a404e4031f9ea
URL:
https://github.com/llvm/llvm-project/commit/8679d1b51bd91d638ac3babba03a404e4031f9ea
DIFF:
https://github.com/llvm/llvm-project/commit/8679d1b51bd91d638ac3babba03a404e4031f9ea.dif
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/109920
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