[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -3186,190 +3186,24 @@ define i32 @bcmp_size_16(ptr %s1, ptr %s2) nounwind { ; ; CHECK-ALIGNED-RV32-V-LABEL: bcmp_size_16: ; CHECK-ALIGNED-RV32-V: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-V-NEXT:lbu a2, 1(a0) -; CHECK-ALIGNED-RV32-V-NEXT:lbu a3, 0(a0) -; CHECK-AL

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -2504,5 +2504,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { Options.LoadSizes = {8, 4, 2, 1}; else Options.LoadSizes = {4, 2, 1}; + if (IsZeroCmp && ST->hasVInstructions()) { +unsigned RealMinVLen = ST->getRealMinVLen() / 8;

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Skip update if an AA is at its initial state (PR #114726)

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/114726 >From 4e380599d038e8269c100f7a252331d5db9dffb7 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Sun, 3 Nov 2024 19:35:26 -0500 Subject: [PATCH] [AMDGPU][Attributor] Skip update if an AA is at its initial state

[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Skip update if an AA is at its initial state (PR #114726)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Shilei Tian (shiltian) Changes --- Patch is 31.50 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/114726.diff 7 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPUAttributor.

[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Skip update if an AA is at its initial state (PR #114726)

shiltian wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/114726?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)

https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/114724 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)

https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/114724 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)

https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/114746 >From dcf8feee9c8d410b42fa8bed29a15c14bb7d6d2e Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Mon, 4 Nov 2024 06:58:14 + Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions --- llvm/inclu

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From 9859c07861131607e36d3de2ee0d2a9980b8d6da Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [clang] [llvm] [PassBuilder] Add `ThinOrFullLTOPhase` to optimizer pipeline (PR #114577)

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/114577 >From a931d1ad84429798fe01ec76dc77cd221f03d2d4 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Fri, 1 Nov 2024 12:39:52 -0400 Subject: [PATCH] [PassBuilder] Add `ThinOrFullLTOPhase` to optimizer pipeline ---

[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor existing attribute (PR #114438)

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/114438 >From 79f88836a79e63069eb6b7b58fa376bcd2b32303 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Thu, 31 Oct 2024 12:49:07 -0400 Subject: [PATCH] [WIP][AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor existing

[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Skip update if an AA is at its initial state (PR #114726)

https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/114726 None >From b7612eddae0b0808f82bb8bc2e6fd6e34361ae5c Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Sun, 3 Nov 2024 19:35:26 -0500 Subject: [PATCH] [AMDGPU][Attributor] Skip update if an AA is at its initial

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-RV32: # %bb.0: # %entry ; CHECK-RV32-NEXT:addi sp, sp, -16 ; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill -; CHECK-RV32-NEXT:li a2, 31 +; CHECK-RV32-NEXT:

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-RV32: # %bb.0: # %entry ; CHECK-RV32-NEXT:addi sp, sp, -16 ; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill -; CHECK-RV32-NEXT:li a2, 31 +; CHECK-RV32-NEXT:

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-RV32: # %bb.0: # %entry ; CHECK-RV32-NEXT:addi sp, sp, -16 ; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill -; CHECK-RV32-NEXT:li a2, 31 +; CHECK-RV32-NEXT:

[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)

https://github.com/vitalybuka edited https://github.com/llvm/llvm-project/pull/114724 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [PassBuilder] Add `ThinOrFullLTOPhase` to optimizer pipeline (PR #114577)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/114577 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

https://github.com/wangleiat created https://github.com/llvm/llvm-project/pull/114742 This patch adds desired feature flags in JIT compiler to enable hard-float instructions if target supports them and allows to use floats and doubles in lldb expressions. Fited tests: lldb-shell :: Expr/TestAno

[llvm-branch-commits] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

llvmbot wrote: @llvm/pr-subscribers-lldb Author: wanglei (wangleiat) Changes This patch adds desired feature flags in JIT compiler to enable hard-float instructions if target supports them and allows to use floats and doubles in lldb expressions. Fited tests: lldb-shell :: Expr/TestAnonNa

[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/114745 None >From 431e6371f161d0f85c598c789902976e3fa74162 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Wed, 30 Oct 2024 04:59:30 + Subject: [PATCH] [CodeGen][NewPM] Port MachineCycleInfo to NPM --- .../llv

[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/114745?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/114746 None >From 40df066d3c32cdeab9927787f201e0b8a72af0bb Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Mon, 4 Nov 2024 06:58:14 + Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions --- llvm

[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/114746?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff dbedca0302d5624554ed7ff4b45c019ad5972166 431e6371f161d0f85c598c789902976e3fa74162 --e

[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)

llvmbot wrote: @llvm/pr-subscribers-compiler-rt-sanitizer Author: Vitaly Buka (vitalybuka) Changes In C++ it's UB to use undeclared values as enum. And there is support `__ATOMIC_HLE_ACQUIRE` and `__ATOMIC_HLE_RELEASE` need such values. Internal implementation was switched to `class enum`

[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)

https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/114724 In C++ it's UB to use undeclared values as enum. And there is support `__ATOMIC_HLE_ACQUIRE` and `__ATOMIC_HLE_RELEASE` need such values. Internal implementation was switched to `class enum`, where that behav